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Author	SHA1	Message	Date
Miodrag Milanovic	0dd1e43dff	Next dev cycle	2024-11-05 08:23:13 +01:00
Miodrag Milanovic	647d61dd92	Release version 0.47	2024-11-05 07:59:25 +01:00
Akash Levy	f99d5a49a0	Merge pull request #15 from alaindargelas/power_activ_fix ... off by 1 bug	2024-11-04 18:12:05 -08:00
Alain Dargelas	3cb8d6ab03	review and warnings	2024-11-04 18:11:09 -08:00
Alain Dargelas	3aea9cca79	off by 1 bug	2024-11-04 18:03:51 -08:00
Akash Levy	1cba744712	Update	2024-11-04 17:01:41 -08:00
Krystine Sherwin	e4994554fd	Docs: Fix nested list	2024-11-05 13:48:48 +13:00
Akash Levy	41f56efc13	Update yosys-slang dep	2024-11-04 16:48:22 -08:00
Krystine Sherwin	f2517f7599	README: Add note on linting	2024-11-05 13:42:16 +13:00
Krystine Sherwin	b14a651142	Docs: Mention verilator for linting ... Link to verilator in the introduction. Include `verilator --lint-only fifo.v` in the example synth doc. Fix linter warnings in fifo.v.	2024-11-05 13:29:45 +13:00
github-actions[bot]	2999f5589c	Bump version	2024-11-05 00:20:31 +00:00
Krystine Sherwin	ee73a91f44	Remove references to ilang	2024-11-05 12:36:31 +13:00
Akash Levy	ef28e1d758	Bring back fsm	2024-11-04 12:03:56 -08:00
Akash Levy	1eb577120e	Bmux unq	2024-11-04 12:03:53 -08:00
Lofty	52c231dd64	Merge pull request #4697 from georgerennie/george/zero_width_string ... frontends/ast.cc: special-case zero width strings as "\0"	2024-11-04 15:40:04 +00:00
Lofty	3250f2b82b	Merge pull request #4700 from povik/select-list-mod ... Add `select -list-mod`	2024-11-04 15:38:42 +00:00
Lofty	2610ccb8fa	Merge pull request #4702 from povik/cellmatch-derive-luts ... Document `cellmatch -derive_luts` option	2024-11-04 15:38:04 +00:00
Martin Povišer	d752ca4847	Fix test after option change	2024-11-04 16:26:46 +01:00
Martin Povišer	f7400a06cd	Fix test	2024-11-04 16:19:59 +01:00
Martin Povišer	23922faecc	Test new Tcl methods	2024-11-04 16:18:50 +01:00
Martin Povišer	cba9460cba	Split off Tcl APIs into tclapi.cc	2024-11-04 16:17:02 +01:00
George Rennie	84ee345071	pyosys: support ObjRange ... * this adds support for cells(), modules() and wires() that all return ObjRanges, converting them into lists for python	2024-11-04 16:00:01 +01:00
Martin Povišer	cbe73c9047	cellmatch: Visit whiteboxes for -derive_luts	2024-11-04 14:28:46 +01:00
Martin Povišer	c9ed6d8dcf	cellmatch: Rename -lut_attrs to -derive_luts; document option	2024-11-04 14:28:40 +01:00
George Rennie	de728c9824	pyosys generator: ignore attributes ... * this allows log_error, log_file_error and log_cmd_error which are all marked [[noreturn]] to be supported	2024-11-04 14:08:57 +01:00
Martin Povišer	35a20da512	logger: Adjust print	2024-11-04 13:16:40 +01:00
Martin Povišer	7aa3fdab80	select: Add -list-mod option	2024-11-04 13:16:13 +01:00
Akash Levy	2d929f2e99	Put small back on	2024-11-01 19:38:36 -07:00
Akash Levy	a2ea3c1e7a	Fix colon issue	2024-11-01 17:49:29 -07:00
Akash Levy	b7e51a90e4	Disable small	2024-11-01 14:57:16 -07:00
George Rennie	dbfca1bdff	frontends/ast.cc: special-case zero width strings as "\0" ... * Fixes #4696	2024-11-01 17:19:28 +01:00
Emil J	b2d78589e2	Merge pull request #4675 from YosysHQ/emil/pyosys-fix-segfault ... yosys: fix pyosys initialization segfault	2024-11-01 16:40:58 +01:00
Akash Levy	4eb820a7ec	Update opt_balance_tree to separate the splitfanout	2024-10-31 16:36:17 -07:00
Akash Levy	55acb4acca	Fix endif	2024-10-30 09:19:16 -07:00
Akash Levy	0ffb913ef2	Fixing minor things with abc install with readline and yosys-abc copy	2024-10-30 09:14:47 -07:00
Akash Levy	e50c4a47d6	Add back tests	2024-10-30 09:04:08 -07:00
Zbigniew Jędrzejewski-Szmek	26a3478d8d	Drop timestamp in generate_bram_types_sim.py ... I'm working on build reproducibility of Fedora packages, and this patch fixes an issue observed in test rebuilds: the timestamp was set to the actual time of the build, making builds nonreproducible. Other "Generated by" strings do not include a timestamp, so drop it here too.	2024-10-30 08:47:18 +01:00
Akash Levy	0a2ad64147	Makefile	2024-10-30 00:38:15 -07:00
Akash Levy	b4d7812662	Add abc, some techmap passes, make opt_balance_tree only balance add/mul	2024-10-30 00:38:05 -07:00
Akash Levy	6401027ff6	Add pmux2shiftx	2024-10-29 15:00:00 -07:00
Akash Levy	62e27f5a31	Merge pull request #14 from alaindargelas/guard_sig_size_sim_val_mismatch ... Pass no_split_complex_ports to hierarchy command	2024-10-29 13:53:43 -07:00
Alain Dargelas	4dd26490c2	help message	2024-10-29 13:52:46 -07:00
Alain Dargelas	615f523ef4	pass no_split_complex_ports to hierarchy command	2024-10-29 13:37:03 -07:00
Alain Dargelas	cad46d9c66	formating	2024-10-29 10:44:16 -07:00
Alain Dargelas	3e4964a0e4	Guard against sig mismatch	2024-10-29 10:40:20 -07:00
Alain Dargelas	667a07ab56	Guard against sig mismatch	2024-10-29 10:39:21 -07:00
Akash Levy	fd695c475b	Update yosys-slang dep (in sync now!)	2024-10-28 22:45:15 -07:00
Akash Levy	55d4a457f5	Merge branch 'YosysHQ:main' into main	2024-10-28 17:22:47 -07:00
github-actions[bot]	8fb73e18ff	Bump version	2024-10-29 00:21:12 +00:00
Akash Levy	5e606722e3	Get autoidx reset working	2024-10-28 16:30:47 -07:00