mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-05 09:04:08 +00:00
Code Activity

cellmatch: Visit whiteboxes for -derive_luts

Browse source
This commit is contained in:
Martin Povišer 2024-10-19 01:17:43 +02:00
parent c9ed6d8dcf
commit cbe73c9047
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/cellmatch.cc
View file

@ -214,7 +214,7 @@ struct CellmatchPass : Pass {
r.first->second = new Design;
Design *map_design = r.first->second;
for (auto m : d->selected_whole_modules_warn()) {
for (auto m : d->selected_whole_modules_warn(/* visit whiteboxes */derive_luts)) {
std::vector<uint64_t> luts;
if (!derive_module_luts(m, luts))
continue;