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10279 commits 122 branches 59 tags 73 MiB
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Author SHA1 Message Date
Eddie Hung
180cb39395 abc9 to contain time call 2019-11-25 12:35:57 -08:00
Eddie Hung
f50b6422b0 abc9 to no longer to clock partitioning, operate on whole modules only 2019-11-25 12:35:38 -08:00
Eddie Hung
63b7a48fbc clkpart to analyse async flops too 2019-11-25 12:04:11 -08:00
Marcin Kościelnicki
6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Eddie Hung
23ecf12bbf Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-23 10:29:03 -08:00
Eddie Hung
15aa3f460d More oopsies 2019-11-23 10:28:46 -08:00
Eddie Hung
bf1167bc64 Conditioning abc9 on POs not accurate due to cells 2019-11-23 10:26:55 -08:00
Eddie Hung
eb11c06a69 For abc9, run clkpart before ff_map and after abc9 2019-11-23 10:18:22 -08:00
Eddie Hung
7b2bccb3d3 Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-23 10:18:06 -08:00
Eddie Hung
722eeacc09 Print ".en=" only if there is an enable signal 2019-11-23 10:17:31 -08:00
Eddie Hung
907c8aeaef Escape IdStrings 2019-11-23 10:16:56 -08:00
Eddie Hung
165f5cb6cf More sane naming of submod 2019-11-23 10:01:09 -08:00
Eddie Hung
66ff0511a0 Add -set_attr option, -unpart to take attr name 2019-11-23 09:52:17 -08:00
Eddie Hung
fb49da21bd Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-23 08:39:19 -08:00
Eddie Hung
b46e636c91 Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff 2019-11-23 08:38:48 -08:00
Eddie Hung
23fcdd96b3
Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff 
xaig_dff to support async flops $_DFF_[NP][NP][01]_
 2019-11-23 08:22:03 -08:00
Eddie Hung
96941aacbb Do not use log_signal() for empty SigSpec to prevent "{ }" 2019-11-22 23:29:10 -08:00
Eddie Hung
736b96b186 Call submod once, more meaningful submod names, ignore largest domain 2019-11-22 23:16:15 -08:00
Eddie Hung
1851f4b488 Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 23:01:18 -08:00
Eddie Hung
db2268703f
Merge pull request #1520 from pietrmar/fix-1463 
coolrunner2: remove spurious log_pop() call, fixes #1463
 2019-11-22 22:45:40 -08:00
Eddie Hung
d223e11a72 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 22:28:35 -08:00
Eddie Hung
5cd3d3db0a Remove redundant flatten 2019-11-22 22:28:10 -08:00
Martin Pietryka
97b22413e5 coolrunner2: remove spurious log_pop() call, fixes #1463 
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.

Signed-off-by: Martin Pietryka <martin@pietryka.at>
 2019-11-23 06:21:40 +01:00
Eddie Hung
cba3073026 submod to bitty rather bussy, for bussy wires used as input and output 2019-11-22 20:53:58 -08:00
Eddie Hung
08f85e6438 Stray dump 2019-11-22 20:53:48 -08:00
Eddie Hung
900c806d4e Move clkpart into passes/hierarchy 2019-11-22 17:25:53 -08:00
Eddie Hung
2c5dfd802d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:24:45 -08:00
Eddie Hung
8119383f81 Constant driven signals are also an input to submodules 2019-11-22 17:23:51 -08:00
Eddie Hung
4fdcf8f7d7 Add another test with constant driver 2019-11-22 17:23:34 -08:00
Eddie Hung
89a4a4d90f Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:04:33 -08:00
Eddie Hung
573396851a Oops 2019-11-22 17:03:30 -08:00
Eddie Hung
bf7d36627e Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4 Only action if there is more than one clock domain 2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4 Replace TODO 2019-11-22 16:58:08 -08:00
Eddie Hung
74ea438136 Add testcase for signal used as part input part output 2019-11-22 16:52:55 -08:00
Eddie Hung
81548d1ef9 write_xaiger back to working with whole modules only 2019-11-22 16:52:17 -08:00
Eddie Hung
0806b8e398 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 16:50:56 -08:00
Eddie Hung
8779faf789 Cleanup spacing 2019-11-22 16:50:09 -08:00
Eddie Hung
6a52897aee sigmap(wire) should inherit port_output status of POs 2019-11-22 16:48:11 -08:00
Eddie Hung
2ef2e2c040 Add testcase 2019-11-22 16:48:11 -08:00
Eddie Hung
698854955c Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb Brackets 2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5 Entry in Makefile.inc 2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Eddie Hung
450ad0e9ba Add to CHANGELOG 2019-11-22 15:35:51 -08:00
Eddie Hung
856a3dc98d New 'clkpart' to {,un}partition design according to clock/enable 2019-11-22 15:35:51 -08:00
Eddie Hung
2a54fa41c4 Merge branch 'master' of github.com:YosysHQ/yosys 2019-11-22 15:13:18 -08:00