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Code Activity
7053 commits 97 branches 53 tags 41 MiB
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25 commits

Author SHA1 Message Date
Eddie Hung e67e4a5ed6 Support CEM 2019-09-04 10:52:51 -07:00
Eddie Hung 16316aa05d Rename muxAB to postAddMux 2019-09-03 16:24:59 -07:00
Eddie Hung cd002ad3fb Use choices for addAB, now called postAdd 2019-09-03 16:10:16 -07:00
Eddie Hung 2d80866daf Add support for load value into DSP48E1.P 2019-09-03 15:53:10 -07:00
Eddie Hung a09e69dd56 Fine tune xilinx_dsp pattern matcher 2019-08-30 16:18:58 -07:00
Eddie Hung e67f049e3b Remove debug 2019-08-30 15:03:43 -07:00
Eddie Hung 390cf34d0a Add support for ffM 2019-08-30 15:00:56 -07:00
Eddie Hung 4e782f1509 New pmgen requires explicit accept 2019-08-30 11:02:10 -07:00
Eddie Hung c320abc3f4 xilinx_dsp to be sensitive to keep attribute 2019-08-15 12:34:11 -07:00
Eddie Hung 2f04beeeb5 Perform C -> PCIN optimisation after pattern matcher 2019-08-13 17:11:35 -07:00
Eddie Hung ab1d63a565 Check nusers of DSP output, not whole flop 2019-08-09 17:35:13 -07:00
Eddie Hung e83f231927 Cleanup 2019-08-09 15:47:40 -07:00
Eddie Hung 0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00
Eddie Hung 747690a6df Remove muxY and ffY for now 2019-08-08 16:33:37 -07:00
Eddie Hung 2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung 07e50b9c25 Only pack registers if {A,B,P}REG = 0, do not pack $dffe 2019-08-08 10:51:19 -07:00
Eddie Hung 9ad11ea2cc Fine tune ice40_dsp.pmg, add support for packing subsets of registers 2019-07-19 10:57:32 -07:00
Eddie Hung 802470746c Check if RHS is empty first 2019-07-18 15:22:00 -07:00
Eddie Hung 08fe63c61e Improve pattern matcher to match subsets of $dffe? cells 2019-07-18 14:08:18 -07:00
Eddie Hung 79d63479ea Improve A/B reg packing 2019-07-18 13:30:35 -07:00
Eddie Hung 0727b2c902 Fix xilinx_dsp index cast 2019-07-18 13:18:04 -07:00
Eddie Hung 91629ee4b3 Pattern matcher to check pool of bits, not exactly 2019-07-17 12:45:25 -07:00
Eddie Hung 3f677fb0db Signed extension 2019-07-16 15:54:07 -07:00
Eddie Hung 9616dbd125 Add support {A,B,P}REG packing 2019-07-16 14:06:32 -07:00
Eddie Hung dd59375a66 Add xilinx_dsp for register packing 2019-07-15 14:46:31 -07:00