1102 commits

Author	SHA1	Message	Date
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	a66ca0472a	Added Pass:call_newsel API	2013-12-02 12:17:04 +01:00
Clifford Wolf	905eac04f1	Added "history" command	2013-12-02 11:29:39 +01:00
Clifford Wolf	1b3a60976d	Using RTLIL::id2cstr for prompt printing	2013-11-29 11:55:18 +01:00
Clifford Wolf	61412d167f	Improvements in satgen undef handling	2013-11-25 16:50:45 +01:00
Clifford Wolf	bd65e67d8a	Improvements in satgen undef handling	2013-11-25 15:12:01 +01:00
Clifford Wolf	8c3f4b3957	Started implementing undef handling in satgen	2013-11-25 04:51:33 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	c854ad2e7e	Some driver changes/fixes	2013-11-22 14:53:57 +01:00
Clifford Wolf	058ceda6a0	Added more performance measurement infrastructure	2013-11-22 14:08:10 +01:00
Clifford Wolf	18d003254c	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	2013-11-22 04:41:20 +01:00
Clifford Wolf	8e58bb330d	Added SigBit struct and refactored RTLIL::SigSpec::extract	2013-11-22 04:07:13 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	7d52eb0ddb	Added -v<level> option and some minor driver cleanups	2013-11-17 13:26:31 +01:00
Clifford Wolf	0fd3ebdb23	Added information on all internal cell types to internal checker	2013-11-11 00:13:18 +01:00
Clifford Wolf	378cc509cd	Call internal checker more often	2013-11-10 23:24:21 +01:00
Clifford Wolf	223892ac28	Improved user-friendliness of "sat" and "eval" expression parsing	2013-11-09 12:02:27 +01:00
Clifford Wolf	18f9477e95	Added verification of SAT model to "eval -vloghammer_report" command	2013-11-09 11:38:17 +01:00
Clifford Wolf	259cc1391e	More undef-propagation related fixes	2013-11-08 11:40:36 +01:00
Clifford Wolf	81b8f3292e	Removed debug log from const_pow()	2013-11-08 04:43:38 +01:00
Clifford Wolf	fc6dc0d7b8	Fixed handling of power operator	2013-11-07 22:20:00 +01:00
Clifford Wolf	d7cb62ac96	Fixed more extend vs. extend_u0 issues	2013-11-07 19:20:20 +01:00
Clifford Wolf	947bd9b96b	Renamed extend_un0() to extend_u0() and use it in genrtlil	2013-11-07 18:17:10 +01:00
Clifford Wolf	0e1661f84e	Fixed type of sign extension in opt_const $eq/$ne handling	2013-11-07 16:53:28 +01:00
Clifford Wolf	8c523ef81d	Improved undef handling in == and != for ConstEval	2013-11-06 22:25:35 +01:00
Clifford Wolf	6fcbc79b5c	Improved width extension with regard to undef propagation	2013-11-06 21:05:11 +01:00
Clifford Wolf	f839b842a2	Fixed handling of undef values in POS cells in ConstEval	2013-11-06 18:45:31 +01:00
Clifford Wolf	204572d926	Fixed handling of undef values in MUX select input in ConstEval	2013-11-06 17:33:20 +01:00
Clifford Wolf	f94266bb42	Added eval -vloghammer_report mode	2013-11-06 04:14:56 +01:00
Clifford Wolf	27fec4e77c	Fixed sign handling in const eval of sshl and sshr	2013-11-05 10:22:22 +01:00
Clifford Wolf	1dcb683fcb	Write yosys version to output files	2013-11-03 21:41:39 +01:00
Clifford Wolf	f39c0c9928	Fixed get_share_file_name() for installed yosys	2013-10-27 10:05:19 +01:00
Clifford Wolf	73e68fe323	Added API and Makefile rules for share/ files	2013-10-27 09:33:26 +01:00
Clifford Wolf	bd2c8ec886	Added design->full_selection() helper method	2013-10-27 09:30:58 +01:00
Clifford Wolf	e679a5d046	Fixed handling of boolean attributes (passes)	2013-10-24 11:37:54 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Clifford Wolf	8e8f1994b8	Changed NEW_WIRE API to return the wire, not the signal	2013-10-18 14:19:45 +02:00
Clifford Wolf	cc5e379eca	Added RTLIL NEW_WIRE macro	2013-10-18 13:25:24 +02:00
Clifford Wolf	e0f693cbb0	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	485e870bcd	Added version info to yosys command and added -V option	2013-08-20 09:48:12 +02:00
Clifford Wolf	a860efa8ac	Implemented same div-by-zero behavior as found in other synthesis tools	2013-08-15 21:00:06 +02:00
Clifford Wolf	78658199e6	Fixed signed div/mod in const eval (rounding and stuff)	2013-08-15 18:23:42 +02:00
Clifford Wolf	2f3da54f26	Added sat -ignore_div_by_zero switch	2013-08-15 11:40:01 +02:00
Clifford Wolf	d0e93e04d1	Added eval -brute_force_equiv_checker_x mode	2013-08-15 11:09:30 +02:00
Clifford Wolf	ccf36cb7d8	Added SAT support for $div and $mod cells	2013-08-11 16:27:15 +02:00
Clifford Wolf	a5836af172	Added "clean -purge" and ";;;" support	2013-08-11 13:59:14 +02:00