3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-29 18:52:30 +00:00

Remove auto_wire framework (smarter than the verilog standard)

This commit is contained in:
Clifford Wolf 2013-11-24 17:29:11 +01:00
parent 609caa23b5
commit f71e27dbf1
9 changed files with 5 additions and 126 deletions

View file

@ -265,11 +265,6 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString,
log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
}
void RTLIL::Module::update_auto_wires(std::map<RTLIL::IdString, int>)
{
log_error("Module `%s' has automatic wires bu no HDL backend to handle it!\n", id2cstr(name));
}
size_t RTLIL::Module::count_id(RTLIL::IdString id)
{
return wires.count(id) + memories.count(id) + cells.count(id) + processes.count(id);
@ -779,7 +774,6 @@ RTLIL::Wire::Wire()
port_id = 0;
port_input = false;
port_output = false;
auto_width = false;
}
RTLIL::Memory::Memory()

View file

@ -265,7 +265,6 @@ struct RTLIL::Module {
RTLIL_ATTRIBUTE_MEMBERS
virtual ~Module();
virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters);
virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
virtual size_t count_id(RTLIL::IdString id);
virtual void check();
virtual void optimize();
@ -283,7 +282,7 @@ struct RTLIL::Module {
struct RTLIL::Wire {
RTLIL::IdString name;
int width, start_offset, port_id;
bool port_input, port_output, auto_width;
bool port_input, port_output;
RTLIL_ATTRIBUTE_MEMBERS
Wire();
};