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https://github.com/YosysHQ/yosys
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Fixed more extend vs. extend_u0 issues
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parent
02f4f89fdb
commit
d7cb62ac96
3 changed files with 20 additions and 11 deletions
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@ -33,6 +33,17 @@ static void extend(RTLIL::Const &arg, int width, bool is_signed)
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arg.bits.push_back(padding);
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}
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static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
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{
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RTLIL::State padding = RTLIL::State::S0;
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if (arg.bits.size() > 0 && is_signed)
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padding = arg.bits.back();
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while (int(arg.bits.size()) < width)
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arg.bits.push_back(padding);
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}
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static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
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{
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BigInteger result = 0, this_bit = 1;
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@ -117,7 +128,7 @@ RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, boo
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result_len = arg1.bits.size();
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RTLIL::Const arg1_ext = arg1;
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extend(arg1_ext, result_len, signed1);
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extend_u0(arg1_ext, result_len, signed1);
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (size_t i = 0; i < size_t(result_len); i++) {
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@ -138,8 +149,8 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
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if (result_len < 0)
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result_len = std::max(arg1.bits.size(), arg2.bits.size());
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extend(arg1, result_len, signed1);
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extend(arg2, result_len, signed2);
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extend_u0(arg1, result_len, signed1);
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extend_u0(arg2, result_len, signed2);
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (size_t i = 0; i < size_t(result_len); i++) {
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@ -338,11 +349,9 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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RTLIL::Const arg2_ext = arg2;
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RTLIL::Const result(RTLIL::State::S0, result_len);
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while (arg1_ext.bits.size() < arg2_ext.bits.size())
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arg1_ext.bits.push_back(signed1 && signed2 && arg1_ext.bits.size() > 0 ? arg1_ext.bits.back() : RTLIL::State::S0);
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while (arg2_ext.bits.size() < arg1_ext.bits.size())
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arg2_ext.bits.push_back(signed1 && signed2 && arg2_ext.bits.size() > 0 ? arg2_ext.bits.back() : RTLIL::State::S0);
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int width = std::max(arg1_ext.bits.size(), arg2_ext.bits.size());
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extend_u0(arg1_ext, width, signed1 && signed2);
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extend_u0(arg2_ext, width, signed1 && signed2);
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RTLIL::State matched_status = RTLIL::State::S1;
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for (size_t i = 0; i < arg1_ext.bits.size(); i++) {
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