2107 commits

Author	SHA1	Message	Date
Eddie Hung	1d88887cfd	Add a unique argument to pmgen's nusers()	2019-08-23 14:32:17 -07:00
Eddie Hung	8ecfd55d5a	Update doc	2019-08-23 14:16:41 -07:00
Eddie Hung	3d7f4aa0c8	Remove (* init *) entry when consumed into SRL	2019-08-23 13:56:01 -07:00
Eddie Hung	a1f78eab04	indo -> into	2019-08-23 13:15:41 -07:00
Eddie Hung	5939ffdc07	Forgot to slice	2019-08-23 13:06:59 -07:00
Eddie Hung	242b3083ea	Cope with possibility that D could connect to Q on same cell	2019-08-23 13:06:31 -07:00
Eddie Hung	18b64609c2	xilinx_srl to use 'slice' features of pmgen for word level	2019-08-23 12:22:06 -07:00
Eddie Hung	f4fd41d5d2	Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl	2019-08-23 11:35:06 -07:00
Eddie Hung	78b7d8f531	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-23 11:32:44 -07:00
Clifford Wolf	55bf8f69e0	Fix port hanlding in pmgen ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:26:54 +02:00
Clifford Wolf	adb81ba386	Add pmgen slices and choices ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:15:50 +02:00
Eddie Hung	2b37a093e9	In sat: 'x' in init attr should not override constant	2019-08-22 16:42:19 -07:00
Eddie Hung	53fed4f7e9	Actually, there might not be any harm in updating sigmap...	2019-08-22 16:16:56 -07:00
Eddie Hung	cfafd360d5	Add comment as per @cliffordwolf	2019-08-22 16:16:56 -07:00
Eddie Hung	8691596d19	Revert "Try way that doesn't involve creating a new wire" ... This reverts commit 2f427acc9e.	2019-08-22 16:16:34 -07:00
Eddie Hung	5ff75b1cdc	Try way that doesn't involve creating a new wire	2019-08-22 16:16:34 -07:00
Eddie Hung	e1fff34dde	If d_bit already in sigbit_chain_next, create extra wire	2019-08-22 16:16:34 -07:00
Eddie Hung	c50d68653d	Spelling	2019-08-22 16:06:36 -07:00
Eddie Hung	6e8fda8bf0	Add doc	2019-08-22 11:52:24 -07:00
Eddie Hung	cabadb85e2	Add copyright	2019-08-22 11:25:19 -07:00
Eddie Hung	36d94caec1	Remove shregmap -tech xilinx additions	2019-08-22 11:22:09 -07:00
Eddie Hung	9f3ed1726e	pmgen to also iterate over all module ports	2019-08-22 11:15:16 -07:00
Eddie Hung	74bd190d3b	Remove output_bits	2019-08-22 11:14:59 -07:00
Eddie Hung	231ddbf95c	Forgot to set ud_variable.minlen	2019-08-22 11:02:17 -07:00
Eddie Hung	61639d5387	Do not run xilinx_srl_pm in fixed loop	2019-08-22 10:51:04 -07:00
Eddie Hung	7188972645	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-22 10:32:54 -07:00
Eddie Hung	d0b2973413	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-22 10:32:06 -07:00
Eddie Hung	b800059fc1	Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx ... opt_expr to trim A port of $shiftx/$shift	2019-08-22 10:31:27 -07:00
Eddie Hung	9245f0d3f5	Copy-paste typo	2019-08-22 08:43:44 -07:00
Eddie Hung	6f971470f8	Respect opt_expr -keepdc as per @cliffordwolf	2019-08-22 08:37:27 -07:00
Eddie Hung	379f33af54	Handle $shift and Y_WIDTH > 1 as per @cliffordwolf	2019-08-22 08:22:23 -07:00
Eddie Hung	9e31f01b34	Add cover()	2019-08-22 08:06:24 -07:00
Eddie Hung	d0ffe7544c	Canonical form	2019-08-22 08:05:01 -07:00
Eddie Hung	d3a212ff91	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 21:53:55 -07:00
Eddie Hung	7d02d17b16	Reuse var	2019-08-21 19:18:40 -07:00
Eddie Hung	5c8344363f	Revert "Trim shiftx_width when upper bits are 1'bx" ... This reverts commit 7e7965ca7b.	2019-08-21 19:18:27 -07:00
Eddie Hung	c7859531c2	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 19:18:05 -07:00
Eddie Hung	7e7965ca7b	Trim shiftx_width when upper bits are 1'bx	2019-08-21 18:43:17 -07:00
Eddie Hung	ed7be3e6b6	Add comment	2019-08-21 17:36:38 -07:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	6d76ae4c65	Rename pattern to fixed	2019-08-21 15:46:58 -07:00
Eddie Hung	b0a3b430bf	attribute -> attr	2019-08-21 15:44:07 -07:00
Eddie Hung	61b4d7ae13	Use Cell::has_keep_attribute()	2019-08-21 15:41:46 -07:00
Eddie Hung	6fa9e03e4c	xilinx_srl to support FDRE and FDRE_1	2019-08-21 15:35:29 -07:00
Eddie Hung	3c8e8521a6	Fix polarity of EN_POL	2019-08-21 14:42:11 -07:00
Eddie Hung	a980f0d4be	Add CLKPOL == 0	2019-08-21 14:35:40 -07:00
Eddie Hung	1c7d721558	Reject if not minlen from inside pattern matcher	2019-08-21 14:26:24 -07:00
Eddie Hung	cab2bd083e	Get wire via SigBit	2019-08-21 13:47:47 -07:00
Eddie Hung	52fea5b658	Respect \keep on cells or wires	2019-08-21 13:42:03 -07:00
Eddie Hung	5ce0c31d0e	Add init support	2019-08-21 13:05:10 -07:00