mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Forgot to slice

Browse source
This commit is contained in:
Eddie Hung 2019-08-23 13:06:59 -07:00
parent 242b3083ea
commit 5939ffdc07
1 changed files with 2 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/pmgen/xilinx_srl.cc
View file

@ -106,6 +106,7 @@ void run_variable(xilinx_srl_pm &pm)
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
auto last_cell = ud.chain.back().first;
auto last_slice = ud.chain.back().second;
SigSpec initval;
for (const auto &i : ud.chain) {
@ -130,7 +131,7 @@ void run_variable(xilinx_srl_pm &pm)
pm.autoremove(st.shiftx);
Cell *c = last_cell;
SigBit Q = st.first->getPort(ID(Q));
SigBit Q = st.first->getPort(ID(Q))[last_slice];
c->setPort(ID(Q), Q);
if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {