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Author SHA1 Message Date
SergeyDegtyar
17c92dc679 Fix macc test 2019-08-30 15:22:46 +03:00
SergeyDegtyar
94a56c14b7 div_mod test fix 2019-08-30 14:17:03 +03:00
SergeyDegtyar
f4a48ce8e6 fix div_mod test 2019-08-30 13:22:11 +03:00
SergeyDegtyar
86f1375ecd Fix test for counter 2019-08-30 12:38:28 +03:00
Sergey
f23b540b45
Merge branch 'master' into master 2019-08-30 10:29:47 +03:00
SergeyDegtyar
d144748401 Add new tests. 2019-08-30 09:45:33 +03:00
SergeyDegtyar
eb0a5b2293 Remove unnecessary common.v(assertions for testbenches). 2019-08-30 09:17:32 +03:00
SergeyDegtyar
8e3abda193 Remove simulation from run-test.sh (unnecessary paths) 2019-08-30 09:11:03 +03:00
SergeyDegtyar
20f4aea480 Remove simulation from run-test.sh 2019-08-30 08:53:35 +03:00
Eddie Hung
694e30a354
Merge pull request #1337 from YosysHQ/eddie/fix_carry_wrapper 
Fix $__ICE40_CARRY_WRAPPER, restore abc9 functionality
 2019-08-29 22:10:45 -07:00
Sergey
5dda8f39a6
Merge pull request #2 from YosysHQ/master 
Pull from upstream
 2019-08-29 21:09:40 +03:00
Sergey
d360693040
Merge pull request #3 from YosysHQ/Sergey/tests_ice40 
Merge my changes to tests_ice40 branch
 2019-08-29 21:07:34 +03:00
Eddie Hung
1467761060 Fix typo that's gone unnoticed for 5 months!?! 2019-08-29 10:33:28 -07:00
Eddie Hung
25b1670a84 Rename boxes too 2019-08-29 07:03:32 -07:00
Clifford Wolf
89695fd3ab Bump YOSYS_VER 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-29 12:05:26 +02:00
SergeyDegtyar
d588c6898f Add comments for examples from Lattice user guide 2019-08-29 10:49:46 +03:00
Eddie Hung
13ecd8b0df Add run-test.sh too 2019-08-28 18:47:48 -07:00
Eddie Hung
a4f641f230 Do not overwrite LUT param 2019-08-28 18:46:53 -07:00
Eddie Hung
e301a3dadb Add SB_CARRY to ice40_opt test 2019-08-28 18:46:53 -07:00
Eddie Hung
dd42aa87b9 Add ice40_opt test 2019-08-28 18:46:53 -07:00
Eddie Hung
d46d38e4d5 Trailing comma 2019-08-28 17:25:54 -07:00
Eddie Hung
f5b4bc847c Adapt to $__ICE40_CARRY_WRAPPER 2019-08-28 17:25:05 -07:00
Eddie Hung
e569f13870 Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" 
This reverts commit 2aedee1f0e.
 2019-08-28 17:22:44 -07:00
Eddie Hung
2aedee1f0e Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with 
CARRY_WRAPPER in the same way since I0 and I3 could be used
 2019-08-28 17:07:36 -07:00
Eddie Hung
077e9d4ada Update box size and timings 2019-08-28 17:07:24 -07:00
Eddie Hung
129df7184a Update to new $__ICE40_CARRY_WRAPPER 2019-08-28 17:07:07 -07:00
Eddie Hung
b8a9f73089 Comment out *.sh used for testbenches as we have no more 2019-08-28 12:36:20 -07:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch 
Add $dlatch support to async2sync
 2019-08-28 12:36:06 -07:00
Eddie Hung
87d5d9b8c8 Use equiv for memory and dpram 2019-08-28 12:30:35 -07:00
Eddie Hung
ebd0a1875b Use equiv_opt for latches 2019-08-28 12:21:15 -07:00
Eddie Hung
32eef26ee2 Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40 2019-08-28 12:18:32 -07:00
Eddie Hung
9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
David Shah
13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr 
ecp5: Add GSR and SGSR support
 2019-08-28 12:44:02 +01:00
Clifford Wolf
c84fef92df
Merge pull request #1335 from YosysHQ/clifford/paramap 
Add "paramap" pass
 2019-08-28 10:35:47 +02:00
Clifford Wolf
47ffbf554e Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c Add "paramap" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73 Add $dlatch support to async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 09:45:22 +02:00
SergeyDegtyar
fe58790f37 Revert "Add tests for ecp5" 
This reverts commit 2270ead09f.
 2019-08-28 09:49:58 +03:00
SergeyDegtyar
2270ead09f Add tests for ecp5 2019-08-28 09:47:03 +03:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init 
In sat: 'x' in init attr should be ignored
 2019-08-28 00:18:14 +02:00
Marcin Kościelnicki
d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
Eddie Hung
eab3c1432b
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap 
Add clock buffer insertion pass, improve iopadmap.
 2019-08-27 10:19:27 -07:00
Eddie Hung
28133432be Ignore all 1'bx in (* init *) 2019-08-27 09:24:59 -07:00
Eddie Hung
00387f3927 Revert to using clean 2019-08-27 09:24:32 -07:00
SergeyDegtyar
980830f7b8 Revert "Add tests for ecp5 architecture." 
This reverts commit 134d3fea90.
 2019-08-27 18:28:05 +03:00
Marcin Kościelnicki
5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
SergeyDegtyar
134d3fea90 Add tests for ecp5 architecture. 2019-08-27 18:12:18 +03:00
David Shah
fc001b4731 ecp5: Add GSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:07:06 +01:00
SergeyDegtyar
aad9bad326 Add tests for macc and rom; 
Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071;
In both cases synthesized only LUTs and DFFs.
 2019-08-27 13:56:26 +03:00
Clifford Wolf
fdbcf78909 Add "make bumpversion" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-27 10:15:25 +02:00