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fix div_mod test

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SergeyDegtyar 2019-08-30 13:22:11 +03:00
parent 86f1375ecd
commit f4a48ce8e6
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tests/ice40/div_mod.ys
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@ -4,6 +4,6 @@ flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 88 t:SB_LUT4
select -assert-count 62 t:SB_LUT4
select -assert-count 65 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D