4928 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	b329b5a8d0	Revert "techmap: call hierarchy on map files to determine port directions" ... This reverts commit eabbf6d225.	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	3bded38943	hierarchy: tolerance for apparent recursive instances in techmap files	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	c12fff2753	techmap: call hierarchy on map files to determine port directions	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	2bc6ea7f37	memory: add -bram-register	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	b4b5093a14	memory_bram: add -register	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	8ae1d758e2	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	15fa0b77df	connect: remove input ports on conflict	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	2ed06c4f3b	opt_dff: sigma harder, FfDataSigMapped	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	6de3bdc4f4	opt_dff: temporarily disable signorm due to muxtree traversal	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	2c024d5e74	design: fix signorm commit connectivity to design	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	00f46cf9ac	flatten: redo signormalization to work around fanout issue	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	319b9e2a4f	signorm: disable passes that use rewrite_sigspecs	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	0822972e8d	check: stitch info about $connect ports together for driver analysis	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	03ac80054f	abstract: skip $input_port cells	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	6a5620303e	flatten: skip $input_port cells in template module	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	74610ae0ee	signorm: disable in passes that use swap_names	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	51331a3ffd	opt_expr: fix invert_map	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	43944a6e4b	techmap: disable signorm more	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	3833c4eeac	techmap: disable signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	099d9886a7	opt_hier: disable signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	c73f1c9fe9	opt_merge_inc: re add initvals deletion	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	e635affe29	wreduce: fixup initvals after setPort	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	b756c67aba	check: don't fail on $input_port	2026-04-16 15:48:57 +02:00
Jannis Harder	89589cdbd6	WIP half broken snapshot	2026-04-16 15:48:57 +02:00
nella	4506dffa9f	Fix use after free.	2026-04-13 12:48:05 +02:00
nella	fc71719e6e	Rename csa_tree to arith_tree.	2026-04-13 12:48:05 +02:00
nella	c3c577f333	Fix test cases.	2026-04-13 12:48:05 +02:00
nella	135812ab02	Further CSA cleanup.	2026-04-13 12:48:05 +02:00
nella	847a8941e9	Clang-Format CSA tree.	2026-04-13 12:48:05 +02:00
nella	a02c238874	Consolidate Wallace from booth and CSA.	2026-04-13 12:48:05 +02:00
nella	4bbffecf98	Invert.	2026-04-13 12:48:05 +02:00
nella	42c309347b	Clarify.	2026-04-13 12:48:05 +02:00
Emil J. Tywoniak	b6d656e932	csa_tree: move to techmap	2026-04-13 12:48:05 +02:00
Emil J. Tywoniak	b6a8feec22	csa_tree: refactor	2026-04-13 12:48:05 +02:00
nella	67e145618b	Replace utf arrow with ascii arrow.	2026-04-13 12:48:05 +02:00
nella	5d90bcc792	CSA add support for macc and alu cells.	2026-04-13 12:48:05 +02:00
nella	335cce4895	Add sub chain support for csa trees.	2026-04-13 12:48:05 +02:00
nella	e69914b8be	better balancing.	2026-04-13 12:48:05 +02:00
nella	46df888191	impl csa tree.	2026-04-13 12:48:05 +02:00
Lofty	564c617721	Merge pull request #5790 from Eiko-Eira/main ... Fixed typos and incorrect grammar	2026-04-11 03:26:55 +00:00
Emil J	86448c0001	Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef ... Undefine set&reset behavior of $dffsr	2026-04-08 14:22:34 +00:00
Emil J. Tywoniak	41b69df2cb	abc_new: stable TopoSort	2026-04-06 15:09:52 +02:00
Noah Van Dijk	52243e10fb	Fix typo in pmgen/README.md ... Line 161: calulated > calculated	2026-04-02 10:24:31 -05:00
Emil J	cede13a742	Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port ... muxpack: fix wide Y port handling	2026-03-31 10:49:39 +00:00
tondapusili	5b22e64d19	sim: cache sigmap in register_output_step_values	2026-03-24 16:10:11 -07:00
Miodrag Milanović	66306a8ca3	Merge pull request #5769 from Silimate/optimize_sim_pass ... sim: early return from checkSignals in sim mode	2026-03-23 17:19:26 +00:00
Emil J	b44188110b	Merge pull request #5764 from YosysHQ/emil/constmap-error ... constmap: error if no -cell set	2026-03-23 15:15:04 +00:00
tondapusili	69219e6be0	sim: early-return from checkSignals in sim mode	2026-03-20 12:32:49 -07:00
Lofty	f560cba952	Merge pull request #5757 from YosysHQ/lofty/abc9-refactor-3 ... abc9: remove -fast [sc-269]	2026-03-19 08:41:45 +00:00
Lofty	27210627e5	abc9: remove -fast	2026-03-19 07:30:23 +00:00