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signorm: disable passes that use rewrite_sigspecs

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This commit is contained in:
Emil J. Tywoniak 2026-03-17 17:35:57 +01:00
parent 28d9d206d4
commit 319b9e2a4f
6 changed files with 15 additions and 0 deletions
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3
passes/cmds/splitnets.cc
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@ -145,6 +145,9 @@ struct SplitnetsPass : public Pass {
}
extra_args(args, argidx, design);
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
// module_ports_db[module_name][old_port_name] = new_port_name_list
dict<IdString, dict<IdString, vector<IdString>>> module_ports_db;

3
passes/equiv/equiv_miter.cc
View file

@ -319,6 +319,9 @@ struct EquivMiterPass : public Pass {
worker.miter_name = RTLIL::escape_id(args[argidx++]);
extra_args(args, argidx, design);
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
if (design->module(worker.miter_name))
log_cmd_error("Miter module %s already exists.\n", log_id(worker.miter_name));

2
passes/sat/freduce.cc
View file

@ -827,6 +827,8 @@ struct FreducePass : public Pass {
break;
}
extra_args(args, argidx, design);
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
int bitcount = 0;
for (auto module : design->selected_modules()) {

1
passes/techmap/abc9_ops.cc
View file

@ -1894,6 +1894,7 @@ struct Abc9OpsPass : public Pass {
extra_args(args, argidx, design);
// TODO Disabled signorm because swap_names breaks fanout logic
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
if (!valid)

3
passes/techmap/constmap.cc
View file

@ -74,6 +74,9 @@ struct ConstmapPass : public Pass {
if (celltype.empty())
log_cmd_error("Missing required option -cell.\n");
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
if (design->has(celltype)) {
Module *existing = design->module(celltype);
bool has_port = false;

3
passes/techmap/hilomap.cc
View file

@ -105,6 +105,9 @@ struct HilomapPass : public Pass {
}
extra_args(args, argidx, design);
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
for (auto mod : design->selected_modules())
{
module = mod;