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yosys/passes
2026-04-16 15:48:58 +02:00
..
cmds connect: remove input ports on conflict 2026-04-16 15:48:58 +02:00
equiv signorm: disable passes that use rewrite_sigspecs 2026-04-16 15:48:57 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy flatten: redo signormalization to work around fanout issue 2026-04-16 15:48:57 +02:00
memory memory: add -bram-register 2026-04-16 15:48:58 +02:00
opt opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped 2026-04-16 15:48:58 +02:00
pmgen Fix typo in pmgen/README.md 2026-04-02 10:24:31 -05:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat signorm: disable passes that use rewrite_sigspecs 2026-04-16 15:48:57 +02:00
techmap signorm: disable passes that use rewrite_sigspecs 2026-04-16 15:48:57 +02:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00