2149 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	abebf4f2db	signorm: safer indexing if broken invariant	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	f2e5bcb86a	rtlil: publish signorm fanout	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	3010c0fc31	signorm: add timers	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	fb06c1add5	rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	83fa720157	rtlil_bufnorm: more xlog	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	360527af1a	rtlil: fix cloneInto in signorm	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	2fc93aa711	rtlil: sigNormalize Module when added to Design in signorm mode	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	f7149450b4	rtlil_bufnorm: more xlog	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	c40974ee59	rtlil_bufnorm: ignore timing info harder	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	8bcec792e2	ffmerge: initvals signorm compatibility fixup	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	3b1e79d312	timinginfo: special-case $specify2 in signorm invariant	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	aeaf095be4	ff: add FfDataSigMapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	9cc0997658	signorm: remove $input cells when leaving	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	c8faf605f7	signorm: skip const when fixing fanout	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	f6ed20664f	satgen: support $connect	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	b408a059ad	rtlil: add dump_sigmap for hacky signorm debugging	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	9521b22907	timinginfo: disable output wire check due to signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	a7b62c6bc3	rtlil: forbid rewrite_sigspecs in signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	d50f9b7bb1	ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	3b956cea1b	rtlil: fix zero width SigSpec crash in signorm setPort unsetPort	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	479ab70890	rtlil_bufnorm: fix cell deletion deferral bug	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	d93ab0d07f	mem: fix signorm cell type morph	2026-07-17 23:32:34 +02:00
Jannis Harder	b84beb598f	WIP half broken snapshot	2026-07-17 23:32:20 +02:00
Jannis Harder	51fc03688a	WIP remove dead code	2026-07-17 23:31:11 +02:00
nella	dddf137888	Merge pull request #6024 from YosysHQ/nella/scl-build-date ... Include build datetime in scl cache hash	2026-07-13 11:54:45 +00:00
nella	b678c238e4	Include build datetime in scl cache hash.	2026-07-10 12:44:34 +02:00
Michael Baier	58fc67ee66	Adding Width check to resize	2026-07-09 14:34:56 +02:00
Michael Baier	5cd9efefe3	Adding widht checks to backend	2026-07-09 14:34:56 +02:00
Michael Baier	ea41b196da	Adding Widht Limit	2026-07-09 14:34:56 +02:00
Krystine Sherwin	53d1e7615b	Fixup help contents source_file ... Stop empty source files `""` from being exported to json. Move source path fixing to a separate function. `ContentListing::to_json` now takes the source root, recursively calling the source path fixup function on all source paths in the content listing.	2026-07-09 16:05:15 +12:00
Krystine Sherwin	0e763f320b	Fix ContentListing::option source location ... Use a null location instead of referencing `log_help.cc`.	2026-07-09 15:54:17 +12:00
nella	8a2499b544	Merge pull request #5986 from YosysHQ/nella/x-wildcard ... fix case item containing x/z treated as wildcard in proc_rmdead	2026-07-07 08:00:02 +00:00
nella	2b4ec9d57a	Fix covers_nothing.	2026-07-06 13:26:00 +02:00
Miodrag Milanovic	97e2600e5c	Removed rewrite leftovers from log	2026-06-29 08:32:44 +02:00
nella	cb9bfed169	Tighten sig2bits.	2026-06-25 11:14:46 +02:00
Miodrag Milanovic	a689342207	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
Miodrag Milanovic	48a3dcc02a	End of file fix	2026-06-23 07:23:41 +02:00
Miodrag Milanovic	94e43f7675	Remove define since snprintf is supported in MSVC now	2026-06-22 09:50:39 +02:00
nella	c99a037c33	Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745 ... Fix `chparam` values are unsigned when using read_verilog frontend	2026-06-18 16:50:22 +00:00
Miodrag Milanovic	88d4af94cf	Fix share lookup for mingw builds	2026-06-17 10:40:13 +02:00
nella	05805e8b93	Merge pull request #5900 from YosysHQ/nella/arith_tree_improvements ... arith_tree improvements	2026-06-12 14:23:10 +00:00
nella	80011b16b2	Add constant note.	2026-06-12 14:57:53 +02:00
Miodrag Milanovic	ec6266a328	Add one more compatibility logger used in patches for some time	2026-06-12 14:44:26 +02:00
nella	135c2a4113	Get rid of normalize_to_width.	2026-06-11 01:12:35 +02:00
nella	3c6900a570	Depth-schedule finar adder.	2026-06-08 13:47:56 +02:00
nella	11a650c695	Fix depth bug.	2026-06-08 13:47:56 +02:00
nella	a1d841bf64	Rebase + Cmake.	2026-06-08 13:47:56 +02:00
nella	d40431f249	Remove black boxes for now.	2026-06-08 13:29:05 +02:00
nella	5e4e5a1d40	Arith tree - parallel prefix.	2026-06-08 13:29:05 +02:00
nella	862e9fc54e	Remove elarith-fast for now.	2026-06-08 13:29:05 +02:00