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Merge pull request #5900 from YosysHQ/nella/arith_tree_improvements
arith_tree improvements
This commit is contained in:
nella
GitHub
commit
05805e8b93
17 changed files with 1408 additions and 274 deletions
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@ -25,6 +25,8 @@ yosys_core(kernel
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celledges.h
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celltypes.h
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compute_graph.h
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compressor_tree.cc
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compressor_tree.h
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consteval.h
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constids.inc
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cost.cc
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@ -80,7 +82,6 @@ yosys_core(kernel
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topo_scc.h
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utils.h
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version.cc
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wallace_tree.h
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yosys.cc
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yosys_common.h
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yosys_config.h
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328
kernel/compressor_tree.cc
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328
kernel/compressor_tree.cc
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@ -0,0 +1,328 @@
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#include "compressor_tree.h"
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YOSYS_NAMESPACE_BEGIN
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namespace CompressorTree
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{
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std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
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{
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec cout = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout, sum);
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SigSpec carry;
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carry.append(State::S0);
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carry.append(cout.extract(0, width - 1));
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return {sum, carry};
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}
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std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width)
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{
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// First FA: a + b + c -> s0
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SigSpec s0 = module->addWire(NEW_ID, width);
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SigSpec cout_h_full = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout_h_full, s0);
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// cin[0] = 0, cin[i] = cout_h_full[i-1]
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SigSpec cin;
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cin.append(State::S0);
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if (width > 1)
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cin.append(cout_h_full.extract(0, width - 1));
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// Second FA: s0 + d + cin -> sum
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec carry_full = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, s0, d, cin, carry_full, sum);
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SigSpec carry;
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carry.append(State::S0);
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if (width > 1)
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carry.append(carry_full.extract(0, width - 1));
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return {sum, carry};
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}
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std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
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int width_a = GetSize(a);
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int width_b = GetSize(b);
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std::vector<DepthSig> products;
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products.reserve(width_a + 3);
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for (int i = 0; i < width_a; i++) {
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SigBit ai = a[i];
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// b_shifted = (0_i ## b)
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SigSpec b_shifted = SigSpec(State::S0, i);
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b_shifted.append(b);
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b_shifted.extend_u0(width, false);
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// row = b_shifted & replicate(a[i], width)
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SigSpec ai_rep = SigSpec(ai, width);
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SigSpec row = module->addWire(NEW_ID, width);
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module->addAnd(NEW_ID, b_shifted, ai_rep, row);
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// Apply Modified Baugh-Wooley inversions for this row
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bool row_is_bottom = (i == width_a - 1);
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bool any_inversion = (row_is_bottom && b_signed) || a_signed;
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if (any_inversion) {
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std::vector<RTLIL::State> mask(width, RTLIL::State::S0);
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for (int j = 0; j < width_b; j++) {
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int col = i + j;
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if (col < 0 || col >= width)
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continue;
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bool col_is_right = (j == width_b - 1);
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// Flip masks
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bool invert = (row_is_bottom && b_signed) ^ (col_is_right && a_signed);
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if (invert)
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mask[col] = RTLIL::State::S1;
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}
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// Skip the xor entirely if the mask is all zeroes
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bool nonzero = false;
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for (auto s : mask)
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if (s == RTLIL::State::S1) {
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nonzero = true;
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break;
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}
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if (nonzero) {
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SigSpec inverted = module->addWire(NEW_ID, width);
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module->addXor(NEW_ID, row, SigSpec(RTLIL::Const(mask)), inverted);
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row = inverted;
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}
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}
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products.push_back({row, 0});
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}
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// Correction constants
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auto push_one_at = [&](int col) {
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if (col < 0 || col >= width)
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return;
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std::vector<RTLIL::State> v(width, RTLIL::State::S0);
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v[col] = RTLIL::State::S1;
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products.push_back({SigSpec(RTLIL::Const(v)), 0});
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};
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if (b_signed)
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push_one_at(width_a - 1);
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if (a_signed)
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push_one_at(width_b - 1);
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if (a_signed || b_signed)
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push_one_at(width_a + width_b - 1);
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return products;
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}
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std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *out_compressor_count, int *out_final_depth) {
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int levels = 0;
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int fa_count = 0;
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int c42_count = 0;
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int final_depth = 0;
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for (auto &op : operands)
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op.sig.extend_u0(width);
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// Only compress operands ready at current level
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for (int level = 0; operands.size() > 2; level++) {
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// Partition operands into ready and waiting
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std::vector<DepthSig> ready;
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std::vector<DepthSig> waiting;
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ready.reserve(operands.size());
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for (auto &op : operands) {
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if (op.depth <= level)
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ready.push_back(op);
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else
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waiting.push_back(op);
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}
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if (ready.size() < 3) {
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levels++;
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continue;
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}
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// Apply compressors to ready operands
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std::vector<DepthSig> compressed;
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compressed.reserve(ready.size());
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size_t i = 0;
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// PREFER_42 attempts 4:2 grouping greedily (falls back to 3:2 for the residual)
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// FA_ONLY skips
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// DADDA = PREFER_42 (TODO: inspect column heights?)
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bool try_42 = (strategy == Strategy::PREFER_42 || strategy == Strategy::DADDA);
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while (i < ready.size()) {
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size_t remaining = ready.size() - i;
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if (try_42 && remaining >= 4) {
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DepthSig a = ready[i + 0];
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DepthSig b = ready[i + 1];
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DepthSig c = ready[i + 2];
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DepthSig d = ready[i + 3];
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auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
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int dmax = std::max({a.depth, b.depth, c.depth, d.depth});
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compressed.push_back({sum, dmax + 2});
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compressed.push_back({carry, dmax + 2});
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fa_count += 2;
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c42_count += 1;
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i += 4;
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} else if (remaining >= 3) {
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DepthSig a = ready[i + 0];
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DepthSig b = ready[i + 1];
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DepthSig c = ready[i + 2];
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auto [sum, carry] = emit_compressor_32(module, a.sig, b.sig, c.sig, width);
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int dmax = std::max({a.depth, b.depth, c.depth});
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compressed.push_back({sum, dmax + 1});
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compressed.push_back({carry, dmax + 1});
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fa_count += 1;
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i += 3;
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} else {
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// Uncompressed operands pass through to next level
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for (; i < ready.size(); i++)
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compressed.push_back(ready[i]);
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break;
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}
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}
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// Merge compressed with waiting operands
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for (auto &op : waiting)
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compressed.push_back(op);
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operands = std::move(compressed);
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levels++;
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}
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if(out_compressor_count)
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*out_compressor_count = fa_count;
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if (operands.size() == 0) {
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if (out_final_depth)
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*out_final_depth = 0;
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return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
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}
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if (operands.size() == 1) {
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if (out_final_depth)
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*out_final_depth = operands[0].depth;
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return {operands[0].sig, SigSpec(State::S0, width)};
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}
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final_depth = std::max(operands[0].depth, operands[1].depth);
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if (out_final_depth)
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*out_final_depth = final_depth;
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log_assert(operands.size() == 2);
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log(" CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
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return {operands[0].sig, operands[1].sig};
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}
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void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
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{
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int width = GetSize(y);
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log_assert(GetSize(a) == width);
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log_assert(GetSize(b) == width);
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if (width == 0)
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return;
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if (width == 1) {
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module->addXorGate(NEW_ID, a[0], b[0], y[0]);
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return;
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}
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// Bit level gen and prop
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std::vector<SigBit> g_pre(width), p_pre(width);
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for (int i = 0; i < width; i++) {
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SigBit gi = module->addWire(NEW_ID);
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SigBit pi = module->addWire(NEW_ID);
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module->addAndGate(NEW_ID, a[i], b[i], gi);
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module->addXorGate(NEW_ID, a[i], b[i], pi);
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g_pre[i] = gi;
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p_pre[i] = pi;
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}
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// Propagate (g, p) through ceil(log2 W) levels
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std::vector<SigBit> g = g_pre;
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std::vector<SigBit> p = p_pre;
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int num_levels = 0;
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while ((1 << num_levels) < width)
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num_levels++;
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for (int k = 1; k <= num_levels; k++) {
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int s = 1 << (k - 1);
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std::vector<SigBit> g_next(width), p_next(width);
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for (int i = 0; i < width; i++) {
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if (i < s) {
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// Nothing to do
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g_next[i] = g[i];
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p_next[i] = p[i];
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} else {
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// g_i^k = g_i | (p_i & g_(i-s))
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SigBit and_pg = module->addWire(NEW_ID);
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module->addAndGate(NEW_ID, p[i], g[i - s], and_pg);
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SigBit gnew = module->addWire(NEW_ID);
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module->addOrGate(NEW_ID, g[i], and_pg, gnew);
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g_next[i] = gnew;
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// p_i^k = p_i & p_(i-s)
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if (k < num_levels) {
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SigBit pnew = module->addWire(NEW_ID);
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module->addAndGate(NEW_ID, p[i], p[i - s], pnew);
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p_next[i] = pnew;
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} else {
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// Skip last level
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p_next[i] = State::Sx;
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}
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}
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}
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g = std::move(g_next);
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p = std::move(p_next);
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}
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// Sum layer, g[i] is COUT of bit i
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// With CIN 0:
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// sum[0] = p_pre[0]
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// sum[i] = p_pre[i] ^ g[i-1] ...
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module->connect(y[0], p_pre[0]);
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for (int i = 1; i < width; i++)
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module->addXorGate(NEW_ID, p_pre[i], g[i - 1], y[i]);
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}
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Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice) {
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switch (choice) {
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case FinalAdder::DEFAULT:
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case FinalAdder::RIPPLE: {
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return module->addAdd(NEW_ID, a, b, y, false);
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}
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case FinalAdder::PARALLEL_PREFIX: {
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emit_kogge_stone(module, a, b, y);
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return nullptr;
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}
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}
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log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
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return nullptr;
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}
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FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode) {
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switch (mode) {
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case FinalMode::RIPPLE: return FinalAdder::RIPPLE;
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case FinalMode::PREFIX: return FinalAdder::PARALLEL_PREFIX;
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case FinalMode::AUTO:
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default: {
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bool wide = width >= RIPPLE_PREFIX_WIDTH_THRESHOLD;
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bool deep = final_depth >= RIPPLE_PREFIX_DEPTH_THRESHOLD;
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return (wide && deep) ? FinalAdder::PARALLEL_PREFIX : FinalAdder::DEFAULT;
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}
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}
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}
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} // namespace CompressorTree
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YOSYS_NAMESPACE_END
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117
kernel/compressor_tree.h
Normal file
117
kernel/compressor_tree.h
Normal file
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@ -0,0 +1,117 @@
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/**
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* Generalized compressor-tree utilities for multi-operand addition
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*
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* Terminology:
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* - compressor: $fa viewed as reducing N inputs to M outputs (sum + shifted carry) (N:M compressor)
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* - level: A stage of parallel compression operations
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* - depth: Maximum number of N:M compressor levels from any input to a signal
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*
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* Supported compressors:
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* - 3:2 compressor
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* - 4:2 compressor
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*
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* References:
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* - "Some schemes for parallel multipliers" (https://www.acsel-lab.com/arithmetic/arith6/papers/ARITH6_Dadda.pdf)
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* - "Basilisk: Achieving Competitive Performance with Open EDA Tools" (https://arxiv.org/pdf/2405.03523)
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* - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
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* - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
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*/
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#ifndef COMPRESSOR_TREE_H
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#define COMPRESSOR_TREE_H
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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namespace CompressorTree
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{
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// Width and depth thresholds below which a ripple is preferred over parallel-prefix
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// NOTE: Based on "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (Tables 4.7, 4.9) - the threshold
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// should be the point where Kogge-Stone isn't strictly less efficient than RCA
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constexpr int RIPPLE_PREFIX_WIDTH_THRESHOLD = 16;
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constexpr int RIPPLE_PREFIX_DEPTH_THRESHOLD = 5;
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enum class Strategy {
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FA_ONLY, // 3:2 compressors
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PREFER_42, // Prefer 4:2 grouping when >=4 operands ready
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DADDA, // Defer compression until column counts exceed
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};
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struct DepthSig {
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SigSpec sig;
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int depth;
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};
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enum class FinalAdder {
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DEFAULT, // emit $add and let downstream techmap pick
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RIPPLE, // emit $add with explicit narrow hint
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PARALLEL_PREFIX, // emit $add with PARALLEL_PREFIX
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};
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enum class FinalMode {
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AUTO,
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RIPPLE,
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PREFIX,
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};
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std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
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std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
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/**
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* generate_partial_products() - Generate partial products for FMA concat
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* @module:The Yosys module to which the compressors will be added
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* @a: Signal A
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* @b: Signal B
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* @a_signed: Whether signal A is signed
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* @b_signed: Whether signal B is signed
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* @width: Target width
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*
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* Return: Partial-product matrix as a set of depth-0 vectors
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*/
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std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width);
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/**
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* reduce_scheduled() - Reduce multiple operands to two using a compressor tree
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* @module: The Yosys module to which the compressors will be added
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* @operands: Vector of operands to be reduced
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* @sigs: Vector of input signals (operands) to be reduced
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* @width: Target bit-width to which all operands will be zero-extended
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* @strategy: Compression strategy to use
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* @out_compressor_count: Optional pointer to return the number of $fa cells emitted
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* @out_final_depth: Optional pointer to return the final depth of the scheduled tree
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*
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* Return: The final two reduced operands, that are to be fed into an adder
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*/
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std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *out_compressor_count = nullptr, int *out_final_depth = nullptr);
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/**
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* emit_kogge_stone() - Emit a Kogge-Stone parallel-prefix adder
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* @module: The Yosys module to which the gates will be added
|
||||
* @a: Signal A
|
||||
* @b: Signal B
|
||||
* @y: Signal Y = (A + B) mod 2^W
|
||||
*/
|
||||
void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y);
|
||||
|
||||
/**
|
||||
* emit_final_adder() - Emit the final carry-propagate addition between the two reduced vectors
|
||||
* @module:The Yosys module to which the compressors will be added
|
||||
* @a: Signal A
|
||||
* @b: Signal B
|
||||
* @y: Signal Y
|
||||
* @choice: Adder type to instantiate
|
||||
*
|
||||
* Return: Cell* of the emitted instance
|
||||
*/
|
||||
Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice);
|
||||
|
||||
FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode);
|
||||
|
||||
} // namespace CompressorTree
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif // COMPRESSOR_TREE_H
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
/**
|
||||
* Wallace tree utilities for multi-operand addition using carry-save adders
|
||||
*
|
||||
* Terminology:
|
||||
* - compressor: $fa viewed as reducing 3 inputs to 2 outputs (sum + shifted carry) (3:2 compressor)
|
||||
* - level: A stage of parallel compression operations
|
||||
* - depth: Maximum number of 3:2 compressor levels from any input to a signal
|
||||
*
|
||||
* References:
|
||||
* - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
|
||||
* - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
|
||||
*/
|
||||
|
||||
#ifndef WALLACE_TREE_H
|
||||
#define WALLACE_TREE_H
|
||||
|
||||
#include "kernel/sigtools.h"
|
||||
#include "kernel/yosys.h"
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
inline std::pair<SigSpec, SigSpec> emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
|
||||
{
|
||||
SigSpec sum = module->addWire(NEW_ID, width);
|
||||
SigSpec cout = module->addWire(NEW_ID, width);
|
||||
|
||||
module->addFa(NEW_ID, a, b, c, cout, sum);
|
||||
|
||||
SigSpec carry;
|
||||
carry.append(State::S0);
|
||||
carry.append(cout.extract(0, width - 1));
|
||||
return {sum, carry};
|
||||
}
|
||||
|
||||
/**
|
||||
* wallace_reduce_scheduled() - Reduce multiple operands to two using a Wallace tree
|
||||
* @module: The Yosys module to which the compressors will be added
|
||||
* @sigs: Vector of input signals (operands) to be reduced
|
||||
* @width: Target bit-width to which all operands will be zero-extended
|
||||
* @compressor_count: Optional pointer to return the number of $fa cells emitted
|
||||
*
|
||||
* Return: The final two reduced operands, that are to be fed into an adder
|
||||
*/
|
||||
inline std::pair<SigSpec, SigSpec> wallace_reduce_scheduled(Module *module, std::vector<SigSpec> &sigs, int width, int *compressor_count = nullptr)
|
||||
{
|
||||
struct DepthSig {
|
||||
SigSpec sig;
|
||||
int depth;
|
||||
};
|
||||
|
||||
for (auto &s : sigs)
|
||||
s.extend_u0(width);
|
||||
|
||||
std::vector<DepthSig> operands;
|
||||
operands.reserve(sigs.size());
|
||||
for (auto &s : sigs)
|
||||
operands.push_back({s, 0});
|
||||
|
||||
// Number of $fa's emitted
|
||||
if (compressor_count)
|
||||
*compressor_count = 0;
|
||||
|
||||
// Only compress operands ready at current level
|
||||
for (int level = 0; operands.size() > 2; level++) {
|
||||
// Partition operands into ready and waiting
|
||||
std::vector<DepthSig> ready, waiting;
|
||||
for (auto &op : operands) {
|
||||
if (op.depth <= level)
|
||||
ready.push_back(op);
|
||||
else
|
||||
waiting.push_back(op);
|
||||
}
|
||||
|
||||
if (ready.size() < 3)
|
||||
continue;
|
||||
|
||||
// Apply compressors to ready operands
|
||||
std::vector<DepthSig> compressed;
|
||||
size_t i = 0;
|
||||
while (i + 2 < ready.size()) {
|
||||
auto [sum, carry] = emit_fa(module, ready[i].sig, ready[i + 1].sig, ready[i + 2].sig, width);
|
||||
int new_depth = std::max({ready[i].depth, ready[i + 1].depth, ready[i + 2].depth}) + 1;
|
||||
compressed.push_back({sum, new_depth});
|
||||
compressed.push_back({carry, new_depth});
|
||||
if (compressor_count)
|
||||
(*compressor_count)++;
|
||||
i += 3;
|
||||
}
|
||||
// Uncompressed operands pass through to next level
|
||||
for (; i < ready.size(); i++)
|
||||
compressed.push_back(ready[i]);
|
||||
// Merge compressed with waiting operands
|
||||
for (auto &op : waiting)
|
||||
compressed.push_back(op);
|
||||
|
||||
operands = std::move(compressed);
|
||||
}
|
||||
|
||||
if (operands.size() == 0)
|
||||
return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
|
||||
else if (operands.size() == 1)
|
||||
return {operands[0].sig, SigSpec(State::S0, width)};
|
||||
else {
|
||||
log_assert(operands.size() == 2);
|
||||
log(" Wallace tree depth: %d levels of $fa + 1 final $add\n", std::max(operands[0].depth, operands[1].depth));
|
||||
return {operands[0].sig, operands[1].sig};
|
||||
}
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue