1479 commits

Author	SHA1	Message	Date
Eddie Hung	0acc51c3d8	Add temporary abc9 -nomfs and use for synth_xilinx -abc9	2019-10-04 17:35:43 -07:00
Eddie Hung	9c23811839	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
Eddie Hung	9fef1df3c1	Panic over. Model was elsewhere. Re-arrange for consistency	2019-10-04 10:48:44 -07:00
Eddie Hung	4e11782cde	Oops	2019-10-04 10:36:02 -07:00
Eddie Hung	c0f54d3fd5	Ohmilord this wasn't added all this time!?!	2019-10-04 10:34:16 -07:00
David Shah	b424d374db	ecp5: Fix shuffle_enable port ... Signed-off-by: David Shah <dave@ds0.me>	2019-10-01 14:14:46 +01:00
David Shah	7a1538cd36	ecp5: Add support for mapping 36-bit wide PDP BRAMs ... Signed-off-by: David Shah <dave@ds0.me>	2019-10-01 13:46:36 +01:00
Eddie Hung	5b5756b91e	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	2019-09-30 12:52:43 +02:00
Marcin Kościelnicki	4535f2c694	synth_xilinx: Support latches, remove used-up FF init values. ... Fixes #1387.	2019-09-30 12:52:43 +02:00
Eddie Hung	8474c5b366	Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)	2019-09-29 11:26:22 -07:00
Eddie Hung	c372e7baf9	Fix box name	2019-09-27 18:49:45 -07:00
Eddie Hung	b3d8a60cbd	Re-order	2019-09-27 14:32:07 -07:00
Eddie Hung	90236025b7	Missing (* mul2dsp *) for sliceB	2019-09-27 14:21:47 -07:00
Eddie Hung	143f82def2	Missing an '&'	2019-09-26 11:13:08 -07:00
Eddie Hung	84825f9378	Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once	2019-09-26 10:45:14 -07:00
Eddie Hung	033aefc0f4	Typo	2019-09-26 10:34:14 -07:00
Eddie Hung	781dda6175	select once	2019-09-26 10:15:05 -07:00
Eddie Hung	27e5bf5aad	Stop trying to be too smart by prematurely optimising	2019-09-26 09:57:11 -07:00
Eddie Hung	35aaa8d73a	mul2dsp.v slice names	2019-09-25 22:58:55 -07:00
Eddie Hung	34aa3532fb	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	2019-09-25 17:26:47 -07:00
Eddie Hung	a4238637ac	Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" ... This reverts commit 234738b103.	2019-09-25 17:25:44 -07:00
Eddie Hung	f4387e817c	Revert "No need for $__mul anymore?" ... This reverts commit 1d875ac76a.	2019-09-25 17:24:11 -07:00
Eddie Hung	63940913d2	Only wreduce on t:$add	2019-09-25 17:22:04 -07:00
Eddie Hung	234738b103	Remove _TECHMAP_CELLTYPE_ check since all $mul	2019-09-25 16:51:31 -07:00
Eddie Hung	1d875ac76a	No need for $__mul anymore?	2019-09-25 14:06:21 -07:00
Eddie Hung	53ea5daa42	Call 'wreduce' after mul2dsp to avoid unextend()	2019-09-25 14:04:36 -07:00
Eddie Hung	93363c94a2	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	2019-09-25 10:33:16 -07:00
Eddie Hung	b41d2fb4e4	Add (* techmap_autopurge *) to abc_unmap.v too	2019-09-23 22:02:22 -07:00
Eddie Hung	11ac37733d	Add techmap_autopurge to outputs in abc_map.v too	2019-09-23 21:56:28 -07:00
Eddie Hung	27167848f4	Revert "Add a xilinx_finalise pass" ... This reverts commit 23d90e0439.	2019-09-23 19:52:55 -07:00
Eddie Hung	0f53893104	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" ... This reverts commit 67c2db3486.	2019-09-23 19:52:55 -07:00
Eddie Hung	29db96fa1f	Revert "Vivado does not like zero width port connections" ... This reverts commit 895e2befa7.	2019-09-23 19:52:54 -07:00
Eddie Hung	895e2befa7	Vivado does not like zero width port connections	2019-09-23 19:04:07 -07:00
Eddie Hung	67c2db3486	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	2019-09-23 18:56:18 -07:00
Eddie Hung	23d90e0439	Add a xilinx_finalise pass	2019-09-23 18:56:02 -07:00
Eddie Hung	4401e5f142	Grammar	2019-09-20 14:24:31 -07:00
Eddie Hung	ab46d9017b	Fix signedness bug	2019-09-20 10:11:36 -07:00
Eddie Hung	289cf688b7	Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40	2019-09-20 09:02:29 -07:00
Eddie Hung	829e4f5d2c	Revert "Move mul2dsp before wreduce" ... This reverts commit e4f4f6a9d5.	2019-09-20 08:56:16 -07:00
Eddie Hung	e4f4f6a9d5	Move mul2dsp before wreduce	2019-09-20 08:41:40 -07:00
Eddie Hung	691686f92c	Tidy up, fix undriven	2019-09-19 20:04:52 -07:00
Eddie Hung	1602516a8b	$__ABC_REG to have WIDTH parameter	2019-09-19 19:37:45 -07:00
Eddie Hung	e09f80479e	Fix DSP48E1 timing by breaking P path if MREG or PREG	2019-09-19 18:59:28 -07:00
Eddie Hung	362a803779	Revert "Different approach to timing" ... This reverts commit 41256f48a5.	2019-09-19 18:33:38 -07:00
Eddie Hung	41256f48a5	Different approach to timing	2019-09-19 18:33:29 -07:00
Eddie Hung	5ca25b0c59	Suppress $anyseq warnings	2019-09-19 16:27:14 -07:00
Eddie Hung	595fb611a5	Use (* techmap_autopurge *) to suppress techmap warnings	2019-09-19 15:58:01 -07:00
Eddie Hung	c15a35db84	D is 25 bits not 24 bits wide	2019-09-19 15:55:49 -07:00
Eddie Hung	b88f0f6450	Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp	2019-09-19 15:47:41 -07:00
Eddie Hung	95db2489bd	synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2	2019-09-19 14:58:06 -07:00