Miodrag Milanovic
6c65ca4e50
Encode filename unprintable chars
2022-08-08 16:13:33 +02:00
Miodrag Milanovic
2b1aeb44d9
verific - make filepath handling compatible with verilog frontend
2022-08-08 11:57:28 +02:00
Miodrag Milanović
15393442d6
Merge pull request #3089 from YosysHQ/gatecat/liberty_wb
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Add read_liberty -wb
2022-08-01 17:08:04 +02:00
Miodrag Milanovic
52a4a89265
Setting wire upto in verific import
2022-07-29 17:10:31 +02:00
Miodrag Milanović
d19f9d0b66
Update README
2022-07-28 12:32:19 +02:00
Miodrag Milanovic
59b96bb1f8
Upadte documentation and changelog
2022-07-04 11:09:06 +02:00
Miodrag Milanovic
b80976b543
Update to new verific extensions inteface
2022-06-30 11:19:01 +02:00
Archie
7eeb656e2a
Add check for BLIF with no model name
2022-06-22 00:34:49 +01:00
Miodrag Milanovic
1fdbb42fdd
Revert "use new verific extensions library"
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This reverts commit 607e957657
2022-06-21 18:07:47 +02:00
Miodrag Milanovic
607e957657
use new verific extensions library
2022-06-17 16:04:22 +02:00
Miodrag Milanovic
ddc8044655
removed deprecated features code
2022-06-13 10:50:24 +02:00
Miodrag Milanovic
6e8e4b4550
verific: Added "-vlog-libext" option to specify search extension for libraries
2022-06-09 08:57:48 +02:00
Miodrag Milanovic
e35a166353
verific: proper file location for readmem commands
2022-06-04 08:39:50 +02:00
Zachary Snow
a650d9079f
verilog: fix width/sign detection for functions
2022-05-30 16:45:39 -04:00
Jannis Harder
4bfaaea0d5
verilog: fix size and signedness of array querying functions
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genrtlil.cc and simplify.cc had inconsistent and slightly broken
handling of signedness for array querying functions. These functions are
defined to return a signed result. Simplify always produced an unsigned
and genrtlil always a signed 32-bit result ignoring the context.
Includes tests for the the relvant edge cases for context dependent
conversions.
2022-05-30 09:11:31 -04:00
Jannis Harder
b75fa62e9b
verilog: fix $past's signedness
2022-05-25 16:32:08 -04:00
Jannis Harder
cffec1f95f
verilog: fix signedness when removing unreachable cases
2022-05-24 23:03:31 -04:00
Miodrag Milanovic
fdb393b6ce
fix text to fit 80 columns
2022-05-23 19:57:21 +02:00
Miodrag Milanovic
4a5790d404
Update verific command file documentation
2022-05-23 19:35:14 +02:00
Miodrag Milanovic
a6ec5754c6
Use analysis mode if set in file
2022-05-23 19:13:45 +02:00
Jannis Harder
fada77b8cf
verific: Use new value change logic also for $stable of wide signals.
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I missed this in the previous PR.
2022-05-11 13:05:27 +02:00
Jannis Harder
587e09d551
Merge pull request #3305 from jix/sva_value_change_logic
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verific: Improve logic generated for SVA value change expressions
2022-05-09 16:40:34 +02:00
Jannis Harder
a855d62b42
verific: Improve logic generated for SVA value change expressions
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The previously generated logic assumed an unconstrained past value in
the initial state and did not handle 'x values. While the current formal
verification flow uses 2-valued logic, SVA value change expressions
require a past value of 'x during the initial state to behave in the
expected way (i.e. to consider both an initial 0 and an initial 1 as
$changed and an initial 1 as $rose and an initial 0 as $fell).
This patch now generates logic that at the same time
a) provides the expected behavior in a 2-valued logic setting, not
depending on any dont-care optimizations, and
b) properly handles 'x values in yosys simulation
2022-05-09 15:04:01 +02:00
Jannis Harder
96f64f4788
verific: Fix conditions of SVAs with explicit clocks within procedures
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For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
Miodrag Milanovic
422db937d4
Ignore merging past ffs that we are not properly merging
2022-04-29 14:35:02 +02:00
Miodrag Milanovic
1cc281ca6f
verific: allow memories to be inferred in loops (vhdl)
2022-04-18 09:10:28 +02:00
N. Engelhardt
57bc29c64a
verific: allow memories to be inferred in loops
2022-04-15 15:10:48 +02:00
Zachary Snow
bf15dbd0f7
sv: fix always_comb auto nosync for nested and function blocks
2022-04-05 14:43:48 -06:00
Miodrag Milanovic
1a1f529099
Preserve internal wires for external nets
2022-04-01 12:07:15 +02:00
Miodrag Milanovic
bbf65702a1
Fix valgrind tests when using verific
2022-03-30 17:25:53 +02:00
Miodrag Milanovic
703769e494
Properly mark modules imported
2022-03-26 09:43:51 +01:00
Miodrag Milanovic
245ecb0529
Import verific netlist in consistent order
2022-03-25 13:44:16 +01:00
Miodrag Milanović
13655ddccf
Merge pull request #3206 from YosysHQ/micko/quote_remove
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Remove quotes if any from attribute
2022-03-04 16:39:01 +01:00
N. Engelhardt
8fd1b06249
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
Miodrag Milanovic
29293a57bb
Remove quotes if any from attribute
2022-02-16 19:10:13 +01:00
Zachary Snow
15a4e900b2
verilog: support for time scale delay values
2022-02-14 15:58:31 +01:00
Kamil Rakoczy
68c67c40ec
Fix access to whole sub-structs ( #3086 )
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* Add support for accessing whole struct
* Update tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-02-14 14:34:20 +01:00
Zachary Snow
15eb66b99d
verilog: fix dynamic dynamic range asgn elab
2022-02-11 22:54:55 +01:00
Zachary Snow
90bb47d181
verilog: fix const func eval with upto variables
2022-02-11 21:01:51 +01:00
Miodrag Milanović
fc7d78f071
Merge pull request #3164 from zachjs/fix-ast-warn
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fix dumpAst() compilation warning
2022-02-11 16:43:35 +01:00
Miodrag Milanovic
2cef48bf2c
Add ability to override verilog mode for verific -f command
2022-02-09 09:19:25 +01:00
Miodrag Milanovic
0b633b6c2e
Use bmux for NTO1MUX
2022-02-02 16:16:08 +01:00
Zachary Snow
342927732e
fix dumpAst() compilation warning
2022-01-18 00:17:08 -07:00
Zachary Snow
aa35f24290
sv: auto add nosync to certain always_comb local vars
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If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
2022-01-07 22:53:22 -07:00
Zachary Snow
828e85068f
sv: fix size cast internal expression extension
2022-01-07 21:21:02 -07:00
Zachary Snow
8c509a5659
sv: fix size cast clipping expression width
2022-01-03 08:17:35 -07:00
Zachary Snow
7608985d2c
fix width detection of array querying function in case and case item expressions
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I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
2021-12-17 21:22:08 -07:00
Thomas Sailer
4cd2f03e36
preprocessor: do not destroy double slash escaped identifiers
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The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'
This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
2021-12-15 18:06:02 -07:00
Claire Xenia Wolf
313340aed5
Add YOSYS to the implicitly defined verilog macros in verific
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-13 18:20:08 +01:00
Miodrag Milanović
2412497c26
Merge pull request #3102 from YosysHQ/claire/enumxz
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Fix verific import of enum values with x and/or z
2021-12-10 19:36:37 +01:00
