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yosys/frontends
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Jannis Harder 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures 
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
..
aiger Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ast sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
blif Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
json fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
liberty Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil Specify minimum bison version 3.0+ 2021-10-01 21:18:33 -06:00
verific verific: Fix conditions of SVAs with explicit clocks within procedures 2022-05-03 14:13:08 +02:00
verilog verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00