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	verilog: fix size and signedness of array querying functions
genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
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					 4 changed files with 56 additions and 3 deletions
				
			
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			@ -1089,8 +1089,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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			break;
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		}
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		if (str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right") {
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			width_hint = 32;
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			sign_hint = true;
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			width_hint = max(width_hint, 32);
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			break;
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		}
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		if (current_scope.count(str))
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			@ -3450,7 +3450,7 @@ skip_dynamic_range_lvalue_expansion:;
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				else {
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					result = width * mem_depth;
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				}
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				newNode = mkconst_int(result, false);
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				newNode = mkconst_int(result, true);
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				goto apply_newNode;
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			}
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