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103 commits

Author SHA1 Message Date
Miodrag Milanovic
219982941a Create a full copy of read_verilog to read_techlib 2026-06-25 08:48:07 +02:00
Miodrag Milanovic
5f2456ac03 WASI now support filesystem 2026-06-05 09:18:00 +02:00
Emil J. Tywoniak
83c1364eeb read_verilog: remove log I left behind by accident 2026-01-13 18:47:23 +01:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
Robert O'Callahan
d1fd6de6da Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
Emil J. Tywoniak
73747f6928 read_verilog: add -relativeshare for synthesis reproducibility testing 2025-09-16 15:47:35 +02:00
Jannis Harder
193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion 
More varargs conversion
 2025-09-12 18:09:42 +02:00
Robert O'Callahan
f4699e2b10 Remove unnecessary c_str() calls from err_at_loc/warn_at_loc 2025-09-12 06:21:56 +00:00
Robert O'Callahan
e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Emil J. Tywoniak
99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
42b5c14e35 read_verilog, ast: use unified locations in errors and simplify dependencies 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
ecec9a760b ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
8bf750ecbb neater errors, lost in the sauce of source 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
b3bf588966 ast, read_verilog: refactoring 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
KrystalDelusion
547382504b
Update verilog_frontend.cc 
`read_verilog_file_list` should not try to read arguments as selection args.  Without this, trying to pass a file without a `-f|-F` flag is misleading, in the best case giving a warning about the selection not matching any module, or in worst case just doing nothing (if the filename is a valid selection).
 2025-05-08 10:37:04 +12:00
Miodrag Milanovic
406ee4c8d3 read_verilog_file_list: change short help message to start with lower case 2025-04-08 13:20:16 +02:00
Jason Xu
a5f34d04f8 Address comments 2025-03-11 18:50:44 -04:00
Jason Xu
bf1eab565b Fix compile on WASI platform 2025-03-07 20:20:27 -05:00
Jason Xu
ac31bad656 Address all comments 2025-03-07 20:16:28 -05:00
Jason Xu
8ec96ec806 Address most comments 2025-03-07 20:16:28 -05:00
Jason Xu
0678c4dec9 Coding style update 2025-03-07 20:16:28 -05:00
Jason Xu
f62a9be153 Initial file list support 2025-03-07 20:16:28 -05:00
Krystine Sherwin
df95ea824b read_verilog: Add missing defaults for flags 
Fix for YosysHQ/sby#103
 2024-05-07 20:25:36 +02:00
Dag Lem
3ed9030eb4 Optionally suppress output from display system tasks in read_verilog 2024-01-11 13:12:53 +01:00
Marcelina Kościelnicka
801ecc0e1d verilog: Squash a memory leak. 
That was added in ecc22f7fed
 2021-06-14 17:07:41 +02:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Xiretza
0c66141ed2 verilog: rebuild user_type_stack from globals before parsing file 
This was actually a ticking UB bomb: after running the parser, the type
maps contain pointers to children of the current AST, which is
recursively deleted after the pass has executed. This leaves the
pointers in user_type_stack dangling, which just happened to never be a
problem due to another bug that causes typedefs from higher-level type
maps to never be considered.

Rebuilding the type stack from the design's globals ensures the AstNode
pointers are valid.
 2021-03-18 20:52:36 -04:00
Zachary Snow
f71c2dcca6 sv: carry over global typedefs from previous files 
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
 2021-03-17 15:53:52 -04:00
Tom Verbeure
3a8eecebba Fix indents. 2021-01-04 00:17:16 -08:00
Tom Verbeure
bb3439562e Add -nosynthesis flag for read_verilog command. 2021-01-04 00:11:01 -08:00
georgerennie
c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Eddie Hung
22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
Rupert Swarbrick
044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Peter Crozier
ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
Peter Crozier
c06eda2504 Build pkg_user_types before parsing in case of changes in the design. 2020-03-22 18:20:46 -07:00
Peter
0aaa36ca6d Clear pkg_user_types if no packages following a 'design -reset-vlog'. 2020-03-22 18:20:46 -07:00
Peter
14f32028ec Parser changes to support typedef. 2020-03-22 18:20:46 -07:00
Alberto Gonzalez
f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Clifford Wolf
5025aab8c9 Add "verilog_defines -list" and "verilog_defines -reset" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-21 13:35:56 +02:00
Clifford Wolf
ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Eddie Hung
d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Clifford Wolf
84f3a796e1 Include filename in "Executing Verilog-2005 frontend" message, fixes #959 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:37:46 +02:00
Clifford Wolf
3cc95fb4be Add specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
fb7f02be55 New behavior for front-end handling of whiteboxes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 22:24:50 +02:00
Clifford Wolf
f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Clifford Wolf
9b0e7af6d7 Improve read_verilog debug output capabilities 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 20:52:29 +01:00
Clifford Wolf
8fde05dfa5 Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-24 20:51:16 +02:00