Krystine Sherwin
0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
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Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
2025-03-25 12:15:54 +13:00
Emil J. Tywoniak
813f909460
gzip: istream
2025-03-19 13:43:44 +01:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
Jason Xu
a5f34d04f8
Address comments
2025-03-11 18:50:44 -04:00
Jason Xu
98eefc5d1a
Add file list support to read pass
2025-03-07 20:44:21 -05:00
Jason Xu
bf1eab565b
Fix compile on WASI platform
2025-03-07 20:20:27 -05:00
Jason Xu
ac31bad656
Address all comments
2025-03-07 20:16:28 -05:00
Jason Xu
8ec96ec806
Address most comments
2025-03-07 20:16:28 -05:00
Jason Xu
0678c4dec9
Coding style update
2025-03-07 20:16:28 -05:00
Jason Xu
f62a9be153
Initial file list support
2025-03-07 20:16:28 -05:00
Emil J
39aacc95df
Merge pull request #4907 from YosysHQ/emil/fix-clear-preset-latch
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liberty: fix clear and preset latches
2025-03-03 18:53:12 +01:00
Martin Povišer
732ed67014
ast/dpicall: Stop using variable length array
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Fix the compiler warning
variable length arrays in C++ are a Clang extension [-Wvla-cxx-extension]
2025-02-24 17:32:30 +01:00
Emil J. Tywoniak
2b33937ab8
liberty: fix clear and preset latches
2025-02-17 17:36:51 +01:00
KrystalDelusion
cf52cf3009
nowrshmsk: Check for stride==0
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log2(0) returns -inf, which gives undefined behaviour when casting to an int. So catch the case when it's 0 just set the width to 0.
2025-01-31 12:15:53 +13:00
N. Engelhardt
d640157ec4
fix some cases of hdlname being added to objects with private names
2025-01-15 15:56:42 +01:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
N. Engelhardt
378864d33b
bound attributes: handle vhdl null ranges
2024-12-12 11:42:39 +01:00
N. Engelhardt
03033ab6d4
add more tests for bounds attributes, fix attributes appearing in verilog
2024-12-11 16:11:02 +01:00
Martin Povišer
ea38fcca5e
Merge pull request #4737 from povik/abc_new-design-boxes
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Support `abc9_box` on ordinary modules in abc_new
2024-12-10 20:07:56 +01:00
Martin Povišer
e9c7967d1e
Merge pull request #4804 from povik/read_liberty-comb-cells
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read_liberty: Revisit for abc9 whiteboxes
2024-12-10 17:50:21 +01:00
Martin Povišer
6b343c2600
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
Martin Povišer
a353b8fff0
read_liberty: Directly set abc9_box on fitting cells
2024-12-09 15:43:41 +01:00
Miodrag Milanovic
7d4aff618f
verific: Disable module existence check during static elaboration
2024-12-06 15:59:09 +01:00
Martin Povišer
cf0a583f40
read_xaiger2: Rm debug print
2024-12-05 18:33:20 +01:00
Martin Povišer
5dffdd229c
read_liberty: Redo unit delay; add simple_comb_cell attr
2024-12-05 18:31:24 +01:00
KrystalDelusion
c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings
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Reduce number of warnings
2024-12-05 09:16:06 +13:00
Krystine Sherwin
e634e9c26b
aiger2: Resolve warnings
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- Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE).
- Assign default value of EMPTY_LIT to `a` and `b` for comparison ops.
- Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).
2024-12-03 14:01:57 +13:00
Miodrag Milanovic
912b38eedb
verific: Handle crash when using empty box option
2024-12-02 15:45:12 +01:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int
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`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Martin Povišer
3bab837bc9
Merge pull request #4765 from georgerennie/george/rtlil_case_rule
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read_rtlil: Warn on assigns after switches in case rules
2024-11-28 00:01:21 +01:00
Miodrag Milanović
29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific
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verific: fix blackbox regression and add test case
2024-11-25 15:06:54 +01:00
George Rennie
4a057b3c44
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
Miodrag Milanovic
d6bd521487
verific : VHDL assert DFF initial value set on Verific library patch side
2024-11-21 13:43:26 +01:00
Martin Povišer
1cb5fd08b7
Merge pull request #4682 from povik/read_liberty-extensions
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read_liberty extensions
2024-11-18 14:42:18 +01:00
Mike Inouye
06e3ac4415
Fix bug when setting Verific runtime string flags.
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Signed-off-by: Mike Inouye <mikeinouye@google.com>
2024-11-12 18:46:26 +00:00
Martin Povišer
0d5c412807
read_liberty: s/busses/buses/
2024-11-12 13:33:41 +01:00
Martin Povišer
28aa7b00ee
read_liberty: Start an -ignore_busses option
2024-11-12 13:26:38 +01:00
Martin Povišer
0e96e477a2
read_liberty: Defer handling of re-definitions
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Postpone handling re-definitions to after we have established the cell
is not supposed to be ignored on the grounds of one of the user-provided
flags.
2024-11-12 13:26:38 +01:00
Martin Povišer
c7e8d41600
read_liberty: Set area capacitance attributes
2024-11-12 13:26:38 +01:00
Miodrag Milanovic
df391f5816
verific: fix blackbox regression and add test case
2024-11-08 14:57:04 +01:00
Krystine Sherwin
ee73a91f44
Remove references to ilang
2024-11-05 12:36:31 +13:00
George Rennie
dbfca1bdff
frontends/ast.cc: special-case zero width strings as "\0"
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* Fixes #4696
2024-11-01 17:19:28 +01:00
Emil J. Tywoniak
81bbde62ca
verilog_parser: silence yynerrs warning
2024-10-15 08:32:55 -04:00
Emil J
caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip
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Represent string constants as strings
2024-10-14 06:42:54 -07:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Miodrag Milanovic
8d2b63bb8a
Set VHDL assert condition initial state if fed by FF
2024-10-11 16:32:21 +02:00
Martin Povišer
0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay
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read_liberty: Optionally import unit delay arcs
2024-10-07 16:11:51 +02:00
