450 commits

Author	SHA1	Message	Date
Eddie Hung	e67e4a5ed6	Support CEM	2019-09-04 10:52:51 -07:00
Eddie Hung	80aec0f006	st.ffP from if to assert	2019-09-03 16:37:59 -07:00
Eddie Hung	16316aa05d	Rename muxAB to postAddMux	2019-09-03 16:24:59 -07:00
Eddie Hung	cd002ad3fb	Use choices for addAB, now called postAdd	2019-09-03 16:10:16 -07:00
Eddie Hung	2d80866daf	Add support for load value into DSP48E1.P	2019-09-03 15:53:10 -07:00
Eddie Hung	682153de4b	Process post-adder first since C could be used for load-P	2019-09-03 14:57:59 -07:00
Eddie Hung	97d11708e0	Use feedback path for MACC	2019-09-03 14:37:32 -07:00
Eddie Hung	4aa505d1b2	Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc ... ice40_dsp to allow signed multipliers	2019-09-01 10:11:33 -07:00
Eddie Hung	a09e69dd56	Fine tune xilinx_dsp pattern matcher	2019-08-30 16:18:58 -07:00
Eddie Hung	8f503fe3e6	autoremove ffM	2019-08-30 15:30:04 -07:00
Eddie Hung	e67f049e3b	Remove debug	2019-08-30 15:03:43 -07:00
Eddie Hung	15bab02a1b	ffM before addAB	2019-08-30 15:03:12 -07:00
Eddie Hung	c497114e94	Another oops	2019-08-30 15:02:53 -07:00
Eddie Hung	44a35015b3	Update commented out	2019-08-30 15:01:38 -07:00
Eddie Hung	390cf34d0a	Add support for ffM	2019-08-30 15:00:56 -07:00
Eddie Hung	2983a35dc0	Update comment	2019-08-30 15:00:40 -07:00
Eddie Hung	17b77fd411	Missing dep for test_pmgen	2019-08-30 14:01:07 -07:00
Eddie Hung	89359b6927	Missing dep for test_pmgen	2019-08-30 14:00:40 -07:00
Eddie Hung	723815b384	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-30 13:26:19 -07:00
Eddie Hung	c1459bc748	Do not restrict multiplier to unsigned	2019-08-30 12:22:14 -07:00
Eddie Hung	4e782f1509	New pmgen requires explicit accept	2019-08-30 11:02:10 -07:00
Eddie Hung	295c18bd6b	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	2019-08-30 09:50:20 -07:00
David Shah	6919c0f9b0	Merge branch 'master' into xc7dsp	2019-08-30 13:57:15 +01:00
Eddie Hung	4eb5847dbd	Cleanup	2019-08-28 18:10:33 -07:00
Eddie Hung	0af64df10c	Account for D port being a constant	2019-08-28 15:32:38 -07:00
Eddie Hung	52c4655de3	No need to replace Q of slice since $shiftx is autoremove-d	2019-08-28 11:06:11 -07:00
Eddie Hung	11e3eb1009	More cleanup	2019-08-28 10:19:35 -07:00
Eddie Hung	86b538bd02	More cleanup	2019-08-28 10:11:09 -07:00
Eddie Hung	c4d1bd988b	Do not use default_params dict, hardcode default values, cleanup	2019-08-28 10:06:40 -07:00
Eddie Hung	c3e9627afe	Always generate if no match	2019-08-28 09:54:56 -07:00
Eddie Hung	0ebe2c9831	Rename test_pmgen arg xilinx_srl.{fixed,variable}	2019-08-28 09:27:03 -07:00
Eddie Hung	9172d4a674	Missing close bracket	2019-08-26 21:02:52 -07:00
Eddie Hung	54422c5bb4	Remove leftover header	2019-08-26 17:51:13 -07:00
Eddie Hung	e95fb24574	Improve xilinx_srl.fixed generate, add .variable generate	2019-08-26 17:49:08 -07:00
Eddie Hung	45c34c87ee	Account for maxsubcnt overflowing	2019-08-26 17:48:54 -07:00
Eddie Hung	b32d6bf403	Add xilinx_srl_pm.variable to test_pmgen	2019-08-26 17:44:57 -07:00
Eddie Hung	e574edc3e9	Populate generate for xilinx_srl.fixed pattern	2019-08-26 14:21:17 -07:00
Eddie Hung	cf9e017127	Add xilinx_srl_fixed, fix typos	2019-08-26 14:20:06 -07:00
Eddie Hung	7911143827	Create new $__XILINX_SHREG_ cell for variable length too	2019-08-23 18:15:49 -07:00
Eddie Hung	a048fc93e8	Do not allow Q of last cell of variable length SRL to be (* keep *)	2019-08-23 18:15:24 -07:00
Eddie Hung	ee9f6e6243	Also add first.Q to chain_bits since variable length	2019-08-23 18:14:06 -07:00
Eddie Hung	70ce3d0670	Do not enforce !EN_POLARITY on $dffe	2019-08-23 18:11:28 -07:00
Eddie Hung	188b49378a	Create new cell for fixed length SRL	2019-08-23 17:25:30 -07:00
Eddie Hung	e081303ee8	Cleanup FDRE matching	2019-08-23 17:23:52 -07:00
Eddie Hung	54488cfb82	Oops don't need a finally block	2019-08-23 16:39:37 -07:00
Eddie Hung	83e2d87fb8	Keep track of bits in variable length chain, to check for taps	2019-08-23 16:21:10 -07:00
Eddie Hung	f2d4814284	Don't forget $dff has no EN	2019-08-23 16:14:57 -07:00
Eddie Hung	2217d926a9	Same for variable length	2019-08-23 16:13:16 -07:00
Eddie Hung	b1caf7be5e	Filter on en_port for fixed length	2019-08-23 16:09:46 -07:00
Eddie Hung	513af10d77	Check clock is consistent	2019-08-23 15:18:26 -07:00