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Process post-adder first since C could be used for load-P

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This commit is contained in:
Eddie Hung 2019-09-03 14:57:59 -07:00
parent 97d11708e0
commit 682153de4b
1 changed files with 22 additions and 18 deletions
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40
passes/pmgen/xilinx_dsp.cc
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@ -49,8 +49,27 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
Cell *cell = st.dsp;
bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell));
SigSpec C = st.sigC;
SigSpec P = st.sigP;
if (st.addAB) {
log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
SigSpec &opmode = cell->connections_.at("\\OPMODE");
if (st.ffP && C == P) {
C = SigSpec();
opmode[4] = State::S0;
}
else
opmode[4] = State::S1;
opmode[6] = State::S0;
opmode[5] = State::S1;
pm.autoremove(st.addAB);
}
if (st.clock != SigBit())
{
cell->setPort("\\CLK", st.clock);
@ -125,25 +144,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
log("\n");
}
if (st.addAB) {
log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
SigSpec C = st.sigC;
SigSpec &opmode = cell->connections_.at("\\OPMODE");
if (cell->getParam("\\PREG").as_bool() && C == P) {
opmode[4] = State::S0;
}
else {
if (!C.empty()) {
if (GetSize(C) < 48)
C.extend_u0(48, true);
cell->setPort("\\C", C);
opmode[4] = State::S1;
}
opmode[6] = State::S0;
opmode[5] = State::S1;
pm.autoremove(st.addAB);
cell->setPort("\\C", C);
}
if (GetSize(P) < 48)