Martin Povišer
2e587c835f
abc9_exe: Document SC mapping options
2024-10-07 12:03:49 +02:00
Martin Povišer
3b6dcc7bd0
abc9_exe: Remove -genlib option
2024-10-07 12:03:49 +02:00
Martin Povišer
e0a86d5483
abc_new: Start new command for aiger2-based round trip
2024-10-07 12:03:49 +02:00
Martin Povišer
e58a9b6ab6
abc9: Understand ASIC options similar to abc
2024-10-07 12:03:48 +02:00
Martin Povišer
ec42b42bd9
cellmatch: Size the lut attribute
2024-10-02 11:29:54 +02:00
George Rennie
023f029dcf
opt_reduce: keep at least one input to $reduce_or/and cells
2024-09-25 16:21:19 +01:00
George Rennie
58af70624f
opt_demorgan: skip zero width cells
2024-09-24 14:24:59 +01:00
N. Engelhardt
8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail
2024-09-23 15:19:48 +02:00
Martin Povišer
38de01807e
Mark bufnorm experimental
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
80119386c0
Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
8bb70bac8d
Improvements in "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d027ead4b5
Improvements in "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
f4b7ea5fb3
Improvements in "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
32808a0393
Improvements and fixes to "bufnorm" cmd
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d0b5dfa6ef
Add bufnorm pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Emil J
52382c6544
Merge pull request #4583 from YosysHQ/emil/clock_gate
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clockgate: centralize clock enables out of FFs
2024-09-16 15:41:01 +02:00
Emil J. Tywoniak
f193bcf683
clockgate: help string
2024-09-16 14:20:33 +02:00
Emil J. Tywoniak
be7c93ec6d
clockgate: 1-bit const 0
2024-09-16 13:58:27 +02:00
Emil J
a8a92d3469
clockgate: help string
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Co-authored-by: Martin Povišer <povik@cutebit.org>
2024-09-16 13:55:53 +02:00
N. Engelhardt
c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds
2024-09-12 13:04:04 +02:00
Emil J. Tywoniak
1e999a3cb7
clockgate: EN can be a bit on a multi-bit wire
2024-09-11 19:18:25 +02:00
Martin Povišer
34572708d5
Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode
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internal_stats: astnode (sizeof)
2024-09-11 12:21:29 +02:00
Emil J. Tywoniak
1372c47036
internal_stats: astnode (sizeof)
2024-09-11 11:34:20 +02:00
Emil J. Tywoniak
8b464341c2
clockgate: no initvals
2024-09-11 10:24:48 +02:00
Roland Coeurjoly
bdc43c6592
Add left and right bound properties to wire. Add test. Fix printing
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for signed attributes
Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-09-10 12:52:42 +02:00
Emil J. Tywoniak
7e473299bd
clockgate: bail on constant signals
2024-09-09 21:20:19 +02:00
Emil J. Tywoniak
e64fceef70
clockgate: prototype clock gating
2024-09-09 15:00:54 +02:00
Hoa Nguyen
c1205ebc42
Initialize area stats in stat pass
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Currently, the area variables in the stat struct are not initialized.
This caused the area stats occasionally being an erroneous value.
Signed-off-by: Hoa Nguyen <hnpl@google.com>
2024-09-07 21:30:58 -07:00
Miodrag Milanović
b20df72e1e
Merge pull request #4536 from YosysHQ/functional
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Functional Backend
2024-09-06 10:05:04 +02:00
Emil J. Tywoniak
14b9155492
internal_stats: fix doc build by adding a help string
2024-09-05 11:22:21 +02:00
Martin Povišer
68fbca8769
Merge pull request #4554 from YosysHQ/emil/devstat
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internal_stats: init, report current memory consumption on linux and mac
2024-09-03 21:06:46 +02:00
Emil J. Tywoniak
0ce7631956
internal_stats: init, report current memory consumption on linux and mac
2024-09-03 19:28:24 +02:00
George Rennie
bdb5d45591
proc_dff: respect sync rule priorities when generating complex dffsrs
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* This fixes #4560 , where previously the order that sync rules were
processed in depended on the order they were pulled out of a std::map.
This PR changes this to process them in the order they are found in,
respecting the priorities among the async signals
2024-08-28 15:48:07 +01:00
N. Engelhardt
0fc5812dcd
Merge pull request #4541 from YosysHQ/krys/compiler-warnings
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Resolve (some) compiler warnings
2024-08-26 15:04:16 +02:00
Emily Schmidt
850b3a6c29
convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h
2024-08-21 11:04:08 +01:00
Emily Schmidt
8c0f625c3a
functional backend: topological sort starts with the output and next states nodes, other nodes get deleted
2024-08-21 11:03:29 +01:00
Emily Schmidt
bdb59ffc8e
add -fst-noinit flag to sim for not initializing the state from the fst file
2024-08-21 11:03:29 +01:00
Emily Schmidt
dd5ec84a26
fix bugs in drivertools
2024-08-21 11:01:09 +01:00
Jannis Harder
d4e3daa9d0
ComputeGraph datatype for the upcoming functional backend
2024-08-21 11:01:09 +01:00
Jannis Harder
68c3a47945
WIP temporary drivertools example
2024-08-21 11:01:08 +01:00
Emil J
e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix
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peepopt: avoid shift-amount underflow
2024-08-19 15:45:46 +02:00
Krystine Sherwin
7b47f645d7
Address warnings
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- Setting default values
- Fixing mismatched types
- Guarding unused var
2024-08-16 04:30:31 +12:00
Martin Povišer
3057c13a66
Improve libparse encapsulation
2024-08-13 18:47:36 +02:00
Martin Povišer
78382eaa6f
libparse: Adjust whitespace
2024-08-13 18:47:36 +02:00
Martin Povišer
4c3203866f
exec: Add missing newline
2024-08-07 13:02:00 +02:00
George Rennie
236c69bed4
clk2fflogic: run peepopt -formalclk before processing design
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* this attempts to rewrite clock gating patterns into a form that is
less likely to introduce combinational loops with clk2fflogic
* can be disabled with -nopeepopt which is useful for testing
clk2fflogic
2024-08-07 10:14:04 +01:00
George Rennie
2cb3b6e9b8
peepopt: add formal only peepopt to rewrite latches to ffs in clock gates
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* this is gated behind the -formalclk flag, which also disables the other
synthesis focused optimizations
2024-08-07 10:01:45 +01:00
Miodrag Milanovic
6d98418f3d
Set ranges on exported wires in VCD and FST
2024-08-02 15:23:00 +02:00
Emil J
92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy
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cost: add keep_hierarchy pass with min_cost argument
2024-07-29 16:33:08 +02:00
N. Engelhardt
9f869b265c
Merge pull request #4474 from tony-min-1/mchp
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Add PolarFire FPGA support
2024-07-29 15:28:44 +02:00
