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Code Activity
14834 commits 94 branches 53 tags 45 MiB
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186 commits

Author SHA1 Message Date
Eddie Hung
c7aa2c6b79 Cleanup 2019-11-27 01:01:24 -08:00
Eddie Hung
cb05fe0f70 Check for nullptr 2019-11-27 00:51:39 -08:00
Eddie Hung
d960feeeb0 Stray log_dump 2019-11-27 00:50:25 -08:00
Eddie Hung
8c813632b6 Revert "submod to bitty rather bussy, for bussy wires used as input and output" 
This reverts commit cba3073026.
 2019-11-27 00:48:22 -08:00
Eddie Hung
969f511415 Promote output wires in sigmap so that can be detected 2019-11-26 23:39:14 -08:00
Eddie Hung
5e487b103c Fix submod -hidden 2019-11-26 23:26:25 -08:00
Eddie Hung
435d33c373 Add -hidden option to submod 2019-11-26 23:26:12 -08:00
Eddie Hung
eb666b4677 Update docs with bullet points 2019-11-26 11:12:58 -08:00
Eddie Hung
0d7ba77426 Move \init from source wire to submod if output port 2019-11-25 16:07:47 -08:00
Eddie Hung
cba3073026 submod to bitty rather bussy, for bussy wires used as input and output 2019-11-22 20:53:58 -08:00
Eddie Hung
8119383f81 Constant driven signals are also an input to submodules 2019-11-22 17:23:51 -08:00
Eddie Hung
573396851a Oops 2019-11-22 17:03:30 -08:00
Eddie Hung
6a52897aee sigmap(wire) should inherit port_output status of POs 2019-11-22 16:48:11 -08:00
Eddie Hung
d2306d7b1d Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
Eddie Hung
116c249601 -auto-top should check $abstract (deferred) modules with (* top *) 2019-08-28 19:59:25 -07:00
Eddie Hung
48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung
ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Eddie Hung
234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung
e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Clifford Wolf
3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Clifford Wolf
ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Stefan Biereigel
ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf
ec39cfd0ad Add "hierarchy -chparam" support for non-verific top modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 22:03:43 +02:00
Eddie Hung
eb21bf3651 log_warning_noprefix -> log_warning as per review 2019-05-03 20:53:25 +02:00
Eddie Hung
a27b42e975 WIP -chparam support for hierarchy when verific 2019-05-03 20:53:25 +02:00
Clifford Wolf
f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Clifford Wolf
d0b9b1bece Add "hdlname" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:52:48 +01:00
Clifford Wolf
ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00
Clifford Wolf
c258b99040 Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:41:36 +01:00
Jim Lawson
71bcc4c644 Address requested changes - don't require non-$ name. 
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
 2019-02-22 16:06:10 -08:00
Jim Lawson
5c4a72c43e Fix normal (non-array) hierarchy -auto-top. 
Add simple test.
 2019-02-19 14:35:15 -08:00
Jim Lawson
5c504c5ae6 Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). 2019-02-15 11:31:37 -08:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Ruben Undheim
436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim
c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
Ruben Undheim
458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf
5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf
3ab79a231b Bugfix in handling of array instances with empty ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-31 18:09:31 +02:00
Clifford Wolf
11406a8082 Add "hierarchy -simcheck" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 13:59:13 +02:00
Clifford Wolf
ee3c12d6d9 Chenged "extensions_map" to "extensions_list" in hierarchy.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:12:57 +02:00
Sergi Granell
f93f8aaa11 passes/hierarchy: Reduce code duplication in expand_module 
This also makes it easier to add new file extensions support.

Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
 2018-03-27 09:35:20 +02:00
Clifford Wolf
491c352da7 Add .sv support to "hierarchy -libdir" 2018-03-26 21:19:00 +02:00
Clifford Wolf
446ccf1f05 Bugfix in hierarchy blackbox module port width handling 2018-01-07 16:35:22 +01:00
Clifford Wolf
c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf
2d140a44eb Temporarily derive blackbox modules in hierarchy to evaluate port widths 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-04 13:23:29 +01:00
Clifford Wolf
ca53fba44a Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
Clifford Wolf
b6bd12fade Add error for cell output ports that are connected to constants 2017-07-22 15:08:30 +02:00