Eddie Hung
d439a830c6
Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp
2019-07-19 09:40:47 -07:00
David Shah
80884d6f7b
ice40: Fix test_dsp_model.sh
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:57 +01:00
David Shah
79f14c7514
ice40/cells_sim.v: Fix sign of J and K partial products
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:41 +01:00
Eddie Hung
2168568f43
Use sign_headroom instead
2019-07-19 09:16:13 -07:00
David Shah
3c84271543
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73
Add tests for all combinations of A and B signedness for comb mul
2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe
Don't copy ref if exists already
2019-07-19 08:45:35 -07:00
Eddie Hung
bddd641290
Fix SB_MAC sim model -- do not sign extend internal products?
2019-07-18 21:03:54 -07:00
Eddie Hung
601fac97e4
Add params
2019-07-18 21:02:49 -07:00
Eddie Hung
a777be3091
Merge remote-tracking branch 'origin/master' into ice40dsp
2019-07-18 20:37:39 -07:00
Eddie Hung
0157043b97
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-07-18 20:36:48 -07:00
Eddie Hung
15c2a79ab9
Do not define `DSP_SIGNEDONLY macro if no exists
2019-07-18 16:04:58 -07:00
Eddie Hung
42e40dbd0a
Merge remote-tracking branch 'origin/master' into ice40dsp
2019-07-18 15:45:25 -07:00
Eddie Hung
266c1ae122
synth_ice40 to decompose into 16x16
2019-07-18 15:38:09 -07:00
Eddie Hung
2339b7fc37
mul2dsp to create cells that can be interchanged with $mul
2019-07-18 15:37:35 -07:00
Eddie Hung
e22a752242
Make consistent
2019-07-18 15:21:23 -07:00
Eddie Hung
43616e1414
Update Makefile too
2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Eddie Hung
8326af5418
Fix signed multiplier decomposition
2019-07-18 13:11:26 -07:00
Eddie Hung
5562cb08a4
Use single DSP_SIGNEDONLY macro
2019-07-18 13:09:55 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups
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Assorted synth_intel cleanups from @bwidawsk
2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4
synth_intel: Use stringf
2019-07-18 19:02:23 +01:00
Eddie Hung
2024357f32
Working for unsigned
2019-07-18 10:53:18 -07:00
Dan Ravensloft
50f5e29724
synth_intel: s/not family/no family/
2019-07-18 17:28:21 +01:00
Eddie Hung
d5cd2c80be
Cleanup
2019-07-18 09:20:48 -07:00
Ben Widawsky
999811572a
intel_synth: Fix help message
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cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.
Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:25 +01:00
Ben Widawsky
f950a7a75d
intel_synth: Small code cleanup to remove if ladder
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Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:12 +01:00
Ben Widawsky
809b94a67b
intel_synth: Make family explicit and match
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The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:03 +01:00
Ben Widawsky
060e77c09b
intel_synth: Minor code cleanups
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Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:05:54 +01:00
Dan Ravensloft
c78ab8ebc5
synth_intel: rename for consistency with #1184
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Also fix a typo in the help message.
2019-07-18 16:46:21 +01:00
Eddie Hung
20b7120d66
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-07-18 08:11:33 -07:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels
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synth_{ice40,ecp5}: more sensible pass label naming
2019-07-18 15:34:28 +02:00
David Shah
16b0ccf04c
mul2dsp: Lower partial products always have unsigned inputs
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-18 11:33:37 +01:00
Eddie Hung
e3f8e59f18
Make all operands signed
2019-07-17 14:25:40 -07:00
Eddie Hung
58e63feae1
Update comment
2019-07-17 13:26:17 -07:00
Eddie Hung
8dca8d486e
Fix mul2dsp signedness
2019-07-17 12:44:52 -07:00
Eddie Hung
1b62b82e05
A_SIGNED == B_SIGNED so flip both
2019-07-17 11:34:18 -07:00
David Shah
82153059a1
Merge pull request #1204 from smunaut/fix_1187
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ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
2019-07-17 07:55:26 +01:00
Eddie Hung
0b6d47f8bf
Add DSP_{A,B}_SIGNEDONLY macro
2019-07-16 15:55:13 -07:00
Eddie Hung
c501aa5ee8
Signedness
2019-07-16 15:54:27 -07:00
Sylvain Munaut
f28e38de99
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
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The new mapping introduced in 437fec0d88Fixes #1187
(Diagnosis of the issue by @daveshah1 on IRC)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-07-16 23:57:15 +02:00
Eddie Hung
6390c535ba
Revert drop down to 24x16 multipliers for all
2019-07-16 14:30:25 -07:00
Eddie Hung
569cd66764
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-07-16 14:18:36 -07:00
Eddie Hung
5d1ce04381
Add support for {A,B,P}REG in DSP48E1
2019-07-16 14:05:50 -07:00
whitequark
698ab9beee
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
whitequark
ba099bfe9b
synth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 20:41:51 +00:00
Eddie Hung
7a58ee78dc
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
David Shah
d38df68d26
xilinx: Add correct signed behaviour to DSP48E1 model
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 17:53:08 +01:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
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abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
David Shah
95c8d27b0b
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:47:53 +01:00
