mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-14 21:08:47 +00:00
Code Activity

Missing close bracket

Browse source
This commit is contained in:
Eddie Hung 2019-04-18 17:50:11 -07:00
parent cf66416110
commit 0919f36b88
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
techlibs/ice40/cells_sim.v
View file

@ -118,7 +118,7 @@ endmodule
// SiliconBlue Logic Cells
(* abc_box_id = 22 *
(* abc_box_id = 22 *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];