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Use new -wb flag for ABC flow

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This commit is contained in:
Eddie Hung 2019-04-18 10:32:41 -07:00
parent 79881141e2
commit 4c327cf316
4 changed files with 36 additions and 48 deletions
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12
techlibs/ice40/abc.v
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@ -1,12 +0,0 @@
(* abc_box_id = 1 *)
module SB_CARRY (output CO, input CI, I0, I1);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
(* abc_box_id = 2 *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
// Indicate this is a black-box
assign O = 1'b0;
endmodule

2
techlibs/ice40/cells_sim.v
View file

@ -118,6 +118,7 @@ endmodule
// SiliconBlue Logic Cells
(* abc_box_id = 2 *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@ -126,6 +127,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc_box_id = 1, whitebox *)
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule

10
techlibs/ice40/synth_ice40.cc
View file

@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib +/ice40/cells_sim.v");
run("read_verilog -wb +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -327,12 +327,8 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
}
if (!noabc) {
if (abc == "abc9") {
run("read_verilog +/ice40/abc.v");
run("techmap -map +/techmap.v A:abc_box_id");
run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
run("blackbox A:abc_box_id");
}
if (abc == "abc9")
run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
else
run(abc + " -lut 4", "(skip if -noabc)");
}