mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 08:35:32 +00:00
Code Activity
12586 commits 94 branches 53 tags 44 MiB
Commit graph

348 commits

Author SHA1 Message Date
Eddie Hung
91c3afcab7 Use nonblocking 2019-04-23 13:42:06 -07:00
Eddie Hung
4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Eddie Hung
d7f0700bae Convert to use #945 2019-04-21 15:19:02 -07:00
Luke Wren
71da836300 ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments 2019-04-21 21:40:11 +01:00
Eddie Hung
af4652522f ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set 2019-04-19 21:09:55 -07:00
Eddie Hung
2776925bcf Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
Eddie Hung
19b660ff6e Fix SB_DFF comb model 2019-04-18 23:07:16 -07:00
Eddie Hung
0919f36b88 Missing close bracket 2019-04-18 17:50:11 -07:00
Eddie Hung
cf66416110 Annotate SB_DFF* with abc_flop and abc_box_id 2019-04-18 17:46:53 -07:00
Eddie Hung
ca1eb98a97 Add SB_DFF* to boxes 2019-04-18 17:46:32 -07:00
Eddie Hung
4c327cf316 Use new -wb flag for ABC flow 2019-04-18 10:32:41 -07:00
Eddie Hung
9278192efe Also update Makefile.inc 2019-04-18 09:58:34 -07:00
Eddie Hung
7b6ab937c1 Make SB_LUT4 a blackbox 2019-04-18 09:05:22 -07:00
Eddie Hung
8024f41897 Fix rename 2019-04-18 09:04:34 -07:00
Eddie Hung
ed5e75ed7d Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
Eddie Hung
8fd455c910 Update Makefile.inc too 2019-04-17 15:19:48 -07:00
Eddie Hung
c795e14d25 Reduce to three devices: hx, lp, u 2019-04-17 15:19:02 -07:00
Eddie Hung
5c0853fc51 Add up5k timings 2019-04-17 15:10:39 -07:00
Eddie Hung
3105a8a653 Update error message 2019-04-17 15:07:44 -07:00
Eddie Hung
6f3e5297db Add "-device" argument to synth_ice40 2019-04-17 15:04:46 -07:00
Eddie Hung
671cca59a9 Missing abc_flop_q attribute on SPRAM 2019-04-17 14:44:08 -07:00
Eddie Hung
437fec0d88 Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
Eddie Hung
58847df1b9 Mark seq output ports with "abc_flop_q" attr 2019-04-17 12:27:45 -07:00
Eddie Hung
1eade06671 Also update Makefile.inc 2019-04-17 12:27:02 -07:00
Eddie Hung
4fb9ccfcd8 synth_ice40 to use renamed files 2019-04-17 12:22:03 -07:00
Eddie Hung
42c33db22c Rename to abc.* 2019-04-17 12:15:34 -07:00
Eddie Hung
c1ebe51a75 Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 
This reverts commit a7632ab332.
 2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332 Try using an ICE40_CARRY_LUT primitive to avoid ABC issues 2019-04-17 11:10:04 -07:00
Eddie Hung
17fb6c3522 Fix spacing 2019-04-17 08:40:50 -07:00
Eddie Hung
743c164eee Add SB_LUT4 to box library 2019-04-16 17:34:11 -07:00
Eddie Hung
7980118d74 Add ice40 box files 2019-04-16 16:39:30 -07:00
Eddie Hung
bca3cf6843 Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
Clifford Wolf
9284cf92b8 Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae Fix typo in ice40_braminit help msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit 
iCE40 BRAM primitives init from file
 2019-03-09 13:24:10 -08:00
Sylvain Munaut
5b6f591033 ice40: Run ice40_braminit pass by default 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Sylvain Munaut
e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Elms
cd2902ab1f ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 
EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>
 2019-02-28 16:23:40 -08:00
Eddie Hung
f7c7003a19 Merge remote-tracking branch 'origin/master' into xaig 2019-02-26 13:16:03 -08:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress 
Improve ABC netname preservation
 2019-02-22 01:16:34 +01:00
Eddie Hung
a8803a1519 Merge remote-tracking branch 'origin/master' into xaig 2019-02-21 11:23:00 -08:00
Clifford Wolf
2fe1c830eb Bugfix in ice40_dsp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 13:28:46 +01:00
Clifford Wolf
84999a7e68 Add ice40 test_dsp_map test case generator 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb Add "synth_ice40 -dsp" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185 Improve iCE40 SB_MAC16 model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 12:55:20 +01:00
Clifford Wolf
62493c91b2 Add first draft of functional SB_MAC16 model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-19 14:47:27 +01:00
Eddie Hung
323dd0e608 synth_ice40 to have new -abc9 arg 2019-02-14 13:19:27 -08:00
David Shah
7ef2333497 ice40: Use abc -dress in synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut 
synth: add k-LUT mode
 2019-01-02 15:44:57 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00