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yosys/techlibs/ice40
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Sylvain Munaut e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
..
tests Bugfix in ice40_dsp 2019-02-21 13:28:46 +01:00
.gitignore Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
arith_map.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_init.py Switched to Python 3 2015-08-22 09:59:33 +02:00
brams_map.v Fixed WE/RE usage in iCE40 BRAM mapping 2015-11-24 10:51:34 +01:00
cells_map.v Improving vpr output support. 2018-04-18 16:55:12 -07:00
cells_sim.v ice40: Add ice40_braminit pass to allow initialization of BRAM from file 2019-03-08 00:15:46 +01:00
ice40_braminit.cc ice40: Add ice40_braminit pass to allow initialization of BRAM from file 2019-03-08 00:15:46 +01:00
ice40_ffinit.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
ice40_ffssr.cc ice40: Honor the "dont_touch" attribute in FFSSR pass 2018-12-08 22:46:28 +01:00
ice40_opt.cc Extract ice40_unlut pass from ice40_opt. 2018-12-05 16:30:24 +00:00
ice40_unlut.cc Extract ice40_unlut pass from ice40_opt. 2018-12-05 16:30:24 +00:00
latches_map.v Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Makefile.inc ice40: Add ice40_braminit pass to allow initialization of BRAM from file 2019-03-08 00:15:46 +01:00
synth_ice40.cc Merge pull request #740 from daveshah1/improve_dress 2019-02-22 01:16:34 +01:00