mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-20 07:36:39 +00:00
Code Activity
12730 commits 99 branches 53 tags 43 MiB
Commit graph

20 commits

Author SHA1 Message Date
Miodrag Milanovic 247613e649 synth_nexus to synth_lattice 2023-11-14 12:35:15 +01:00
Miodrag Milanovic 567e803f14 enable ABC9 by default except for XO2/3/3D 2023-11-14 12:23:53 +01:00
Miodrag Milanović 03df7e352f Update techlibs/lattice/synth_lattice.cc 
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2023-11-14 12:00:13 +01:00
Miodrag Milanovic 35d2286767 Add help message for synth_ecp5 2023-11-14 12:00:13 +01:00
Miodrag Milanovic 667c3c0aea Update filenames and location for test script 2023-11-14 12:00:13 +01:00
Miodrag Milanovic 1f563b52e3 Enable synth_ecp5 wrapper and copy sim files for backwards compatibility 2023-11-14 12:00:13 +01:00
Miodrag Milanovic 4a0d1121ea Move diamond tests 2023-11-14 12:00:06 +01:00
Miodrag Milanovic edc663a2d2 Special DP16KD model is required 2023-11-14 12:00:06 +01:00
N. Engelhardt 52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work 
MachXO3 QoR improvements
 2023-11-13 16:56:06 +01:00
Martin Povišer 3ffa4b5e5d synth_lattice: Wire up cmp2softlogic as an option 2023-11-13 10:42:12 +01:00
Martin Povišer fed2720999 synth_lattice: Optimize flip-flop memories better 
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
 2023-11-07 16:29:56 +01:00
Martin Povišer ee3a4ce14d synth_lattice: Merge NOT gates on DFF control signals 
`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
 2023-11-07 16:21:39 +01:00
Miodrag Milanovic 72bec94ef4 Add missing file for XO3D 2023-09-01 10:15:51 +02:00
Miodrag Milanovic 792cf8326e defult nowidelut for xo2/3/3d 2023-08-29 10:08:55 +02:00
Miodrag Milanovic b168ff99d0 fix generated blackboxes for ecp5 2023-08-28 16:26:26 +02:00
Miodrag Milanovic 0756285710 enable more primitives supported with nextpnr 2023-08-25 11:45:25 +02:00
Miodrag Milanovic 3b9ebfa672 Addressed code review comments 2023-08-25 11:10:20 +02:00
Miodrag Milanovic 541c1ab567 add script for blackbox extraction 2023-08-23 11:51:00 +02:00
Miodrag Milanovic e3c15f003e Create synth_lattice 2023-08-23 10:53:21 +02:00
Miodrag Milanovic a8809989c4 ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00