Prevents unintended bumps on the flake.lock and Yosys version on forks (provided the forks synchronize their main after this gets merged).
Update version.yml to use the same style of `if` on the job, rather than on specific actions.
Wheels will still build as a cron job, but won't try to upload if it's a fork.
Currently the order of extraction can vary based on which ABC runs finish first. That's
nondeterministic, therefore bad. Instead, force the processing to happen in the same order
as `assigned_cells`, i.e. the same order we use when not using parallelism. This should
make everything deterministic.
Note that we still allow ABC runs to complete out of order. Out-of-order results are
just not extracted until all the previous runs have completed and their results
extracted.
The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.
There are no functional changes, only renaming.
Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.
We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Modify python wrapper generator script with corner-case handlers such that functions that start with `log_formatted` have the format string coerced to `"%s"` and also have an alias without the `_formatted` part.
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
With the updated bufnorm code, buffered 'z drivers are used as anchor
points for undirected connections. These are currently not supported by
read/write_xaiger2, so we temporarily replace those by roughly
equivalent $tribuf cells which will be handled as blackboxes that
properly roundtrip through the xaiger2 front and backend.
The $input_port cell is added by the bufnorm code to simplify handling
of input ports for new code that uses bufnorm, but the aiger2 backend
does already handle input ports separately, so we just ignore those.
With the previous bufnorm implementation inout ports were not supported
at all, so this didn't matter, but with the new bufnorm implementation
they need to be treated as output ports.
This ensures that entering and leaving bufnorm followed by `opt_clean`
is equivalent to just running `opt_clean`.
Also make sure that 'z-$buf cells get techmapped in a compatible way.
This is a complete rewrite of the RTLIL-kernel-side bufnorm code. This
is done to support inout ports and undirected connections as well as to
allow removal of cells while in bufnorm mode.
This doesn't yet update the (experimental) `bufnorm` pass, so to
manually test the new kernel functionality, it is important to only use
`bufnorm -update` and `bufnorm -reset` which rely entirely on the kernel
functionality. Other modes of the `bufnorm` pass may still fail in the
presence of inout ports or undirected connections.
