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Author SHA1 Message Date
Miodrag Milanovic
247613e649 synth_nexus to synth_lattice 2023-11-14 12:35:15 +01:00
Miodrag Milanovic
567e803f14 enable ABC9 by default except for XO2/3/3D 2023-11-14 12:23:53 +01:00
Miodrag Milanović
03df7e352f Update techlibs/lattice/synth_lattice.cc 
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2023-11-14 12:00:13 +01:00
Miodrag Milanovic
35d2286767 Add help message for synth_ecp5 2023-11-14 12:00:13 +01:00
Miodrag Milanovic
667c3c0aea Update filenames and location for test script 2023-11-14 12:00:13 +01:00
Miodrag Milanovic
1f563b52e3 Enable synth_ecp5 wrapper and copy sim files for backwards compatibility 2023-11-14 12:00:13 +01:00
Miodrag Milanovic
0da1ab0cbd Delete synth_ecp5 2023-11-14 12:00:13 +01:00
Miodrag Milanovic
4a0d1121ea Move diamond tests 2023-11-14 12:00:06 +01:00
Miodrag Milanovic
edc663a2d2 Special DP16KD model is required 2023-11-14 12:00:06 +01:00
Catherine
c11744b4ef
Fix WASI compilation flags for abc. 2023-11-14 03:33:35 +00:00
Catherine
726c501e7e Update WASI compilation flags to include required libraries 2023-11-14 02:05:39 +00:00
github-actions[bot]
46408b5da3 Bump version 2023-11-14 00:15:32 +00:00
N. Engelhardt
8e470add4d
Merge pull request #4029 from YosysHQ/lofty/abc9-again 
ice40, ecp5, gowin: enable ABC9 by default
 2023-11-13 17:29:57 +01:00
N. Engelhardt
52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work 
MachXO3 QoR improvements
 2023-11-13 16:56:06 +01:00
N. Engelhardt
3fef81b537
Merge pull request #4028 from povik/cmp2softlogic 
synth_lattice: Optionally do constant comparisons in soft logic
 2023-11-13 16:53:04 +01:00
Jannis Harder
6cf50d16a8
Merge pull request #3973 from anonkey/master 
cli(tcl): add ability to pass argument to tcl script from cli
 2023-11-13 16:29:05 +01:00
Lofty
7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
N. Engelhardt
04083b4f15
Merge pull request #4027 from YosysHQ/achronix_typo 
Fix typo in help message (Acrhonix -> Achronix)
 2023-11-13 16:04:24 +01:00
Martin Povišer
3ffa4b5e5d synth_lattice: Wire up cmp2softlogic as an option 2023-11-13 10:42:12 +01:00
Martin Povišer
f7d4a855c6 techlibs: Add cmp2softlogic.v to common 2023-11-13 10:42:12 +01:00
Krystine Sherwin
83d2f4f334
techlibs: fix typo in help message 2023-11-13 16:29:52 +13:00
github-actions[bot]
5691cd0958 Bump version 2023-11-08 00:15:30 +00:00
Martin Povišer
fed2720999 synth_lattice: Optimize flip-flop memories better 
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
 2023-11-07 16:29:56 +01:00
Martin Povišer
ee3a4ce14d synth_lattice: Merge NOT gates on DFF control signals 
`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
 2023-11-07 16:21:39 +01:00
N. Engelhardt
63cec22a0c
Merge pull request #3883 from phsauter/peepopt-shiftadd 
peepopt: Add `shiftadd` pattern
 2023-11-07 10:42:15 +01:00
Miodrag Milanovic
8808da243b Next dev cycle 2023-11-07 08:47:34 +01:00
Miodrag Milanovic
cc31c6ebc4 Release version 0.35 2023-11-07 08:45:31 +01:00
Jannis Harder
d415b4d98a cli: Cleanups for tcl argument handling 
* Keep the previous behavior when no tcl script is used
* Do not treat "-" as a flag but as a positional argument
* Keep including <unistd.h> as it's also used for other functions (at
  least for the emscripten build)
* Move the custom getopt implementation into the Yosys namespace to
  avoid potential collisions
 2023-11-06 16:40:13 +01:00
phsauter
3618294bac peepopt: Add assert of consistent shiftadd data 2023-11-06 16:35:00 +01:00
N. Engelhardt
93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr 
memory_libmap: look for ram_style attributes on surrounding signals
 2023-11-06 16:25:38 +01:00
Miodrag Milanović
c58fec636f
Merge pull request #4015 from YosysHQ/log_verific 
Change Verific log callback API
 2023-11-06 16:22:30 +01:00
phsauter
c3b8de54da test: add tests for shiftadd and shiftmul 
This expands the part-select tests with one additional module.
It specifically tests the different variants of the `peepopt`
optimizations `shiftadd` and `shiftmul`.
Not all these cases are actually transformed using `shiftadd`,
including them also checks if the correct variants are rejected.
 2023-11-06 14:01:37 +01:00
Philippe Sauter
b6df900bcc peepopt: Describe shiftadd rule in help message 2023-11-06 14:01:37 +01:00
phsauter
9ca57d9f13 peepopt: fix and refactor shiftadd 
- moved all selection and filtering logic to the match block
- applied less-verbose code suggestions
- removed constraint on number of bits in shift-amount
- added check for possible wrap-arround in the operation
 2023-11-06 14:01:37 +01:00
Philippe Sauter
72c6a01e67 peepopt: Add initial shiftadd pattern 2023-11-06 14:01:37 +01:00
github-actions[bot]
6f1ca68712 Bump version 2023-11-04 00:14:46 +00:00
Lofty
1260766d91
Merge pull request #4020 from YosysHQ/revert-4019-lofty/abc9-by-default 
Revert "ice40, ecp5: enable ABC9 by default"
 2023-11-03 14:53:15 +00:00
Lofty
b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default" 2023-11-03 14:52:52 +00:00
Lofty
deebb82e85
Merge pull request #4019 from YosysHQ/lofty/abc9-by-default 
ice40, ecp5: enable ABC9 by default
 2023-11-03 14:12:56 +00:00
anonkey
ea91f189a3
cli(tcl): add ability to pass argument to tcl script from cli 2023-11-03 12:21:35 +01:00
Lofty
32082477b5 ice40, ecp5: enable ABC9 by default 2023-11-03 08:52:54 +00:00
Miodrag Milanovic
f06d56d224 Handling non-existing location in verific logs 2023-11-03 08:06:16 +01:00
Miodrag Milanovic
4eb18e1f07 change verific log callback api 2023-11-01 08:13:27 +01:00
N. Engelhardt
f9ab6e147a mem: only import attributes from ports if the memory doesn't have them yet 2023-10-30 16:31:53 +01:00
github-actions[bot]
672375ed02 Bump version 2023-10-26 00:14:46 +00:00
Catherine
6ffc315936 cxxrtl: export wire attributes through the C API. 
Co-authored-by: Charlotte <charlotte@lottia.net>
 2023-10-25 16:01:48 +00:00
N. Engelhardt
080da693d1 memory_libmap: update search order for attributes 2023-10-24 13:55:45 +02:00
N. Engelhardt
833b67af80 verific: import attributes on ports 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
 2023-10-20 18:31:41 +02:00
N. Engelhardt
1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Lofty
d21c464ae4
Merge pull request #3946 from rmlarsen/toposort 
Speed up TopoSort by 2.7-3.3x.
 2023-10-17 13:00:18 +01:00