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Enable synth_ecp5 wrapper and copy sim files for backwards compatibility

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This commit is contained in:
Miodrag Milanovic 2023-08-28 16:50:25 +02:00
parent 0da1ab0cbd
commit 1f563b52e3
3 changed files with 15 additions and 2 deletions
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7
Makefile
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@ -575,6 +575,13 @@ $(subst //,/,$(1)/$(notdir $(2))): $(2)
$$(Q) cp "$(YOSYS_SRC)"/$(2) $(subst //,/,$(1)/$(notdir $(2)))
endef
define add_share_file_and_rename
EXTRA_TARGETS += $(subst //,/,$(1)/$(3))
$(subst //,/,$(1)/$(3)): $(2)
$$(P) mkdir -p $(1)
$$(Q) cp "$(YOSYS_SRC)"/$(2) $(subst //,/,$(1)/$(3))
endef
define add_gen_share_file
EXTRA_TARGETS += $(subst //,/,$(1)/$(notdir $(2)))
$(subst //,/,$(1)/$(notdir $(2))): $(2)

8
techlibs/lattice/Makefile.inc
View file

@ -26,3 +26,11 @@ $(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_ff.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_io.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/common_sim.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/ccu2c_sim.vh))
$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_sim_ecp5.v,cells_sim.v))
$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_bb_ecp5.v,cells_bb.v))

2
techlibs/lattice/synth_lattice.cc
View file

@ -496,7 +496,6 @@ struct SynthLatticePass : public ScriptPass
}
} SynthLatticePass;
/*
struct SynthEcp5Pass : public Pass
{
SynthEcp5Pass() : Pass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
@ -511,6 +510,5 @@ struct SynthEcp5Pass : public Pass
Pass::call(design, args);
}
} SynthEcp5Pass;
*/
PRIVATE_NAMESPACE_END