mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
Switching example synth to fifo
Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
This commit is contained in:
Krystine Sherwin
parent
80c78aaad6
commit
742ec78ca3
9 changed files with 2538 additions and 326 deletions
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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DOTS = control_hier.dot control_proc.dot
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DOTS += example_hier.dot
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dots: $(DOTS) example.out
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$(DOTS) example.out: example.v example.ys
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$(YOSYS) example.ys -l example.out -Q
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.PHONY: clean
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clean:
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rm -f *.dot
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@ -1,147 +0,0 @@
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-- Executing script file `example.ys' --
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echo on
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yosys> read_verilog -defer example.v
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1. Executing Verilog-2005 frontend: example.v
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Parsing Verilog input from `example.v' to AST representation.
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Storing AST representation for module `$abstract\example'.
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Storing AST representation for module `$abstract\control'.
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Storing AST representation for module `$abstract\data'.
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Successfully finished Verilog frontend.
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yosys> hierarchy -top control
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2. Executing HIERARCHY pass (managing design hierarchy).
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3. Executing AST frontend in derive mode using pre-parsed AST for module `\control'.
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Generating RTLIL representation for module `\control'.
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3.1. Analyzing design hierarchy..
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Top module: \control
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3.2. Analyzing design hierarchy..
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Top module: \control
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Removing unused module `$abstract\data'.
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Removing unused module `$abstract\control'.
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Removing unused module `$abstract\example'.
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Removed 3 unused modules.
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yosys> show -notitle -format dot -prefix control_hier
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4. Generating Graphviz representation of design.
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Writing dot description to `control_hier.dot'.
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Dumping module control to page 1.
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yosys> proc
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5. Executing PROC pass (convert processes to netlists).
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yosys> proc_clean
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5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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yosys> proc_rmdead
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5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$example.v:43$1 in module control.
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Removed a total of 0 dead cases.
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yosys> proc_prune
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5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 1 redundant assignment.
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Promoted 0 assignments to connections.
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yosys> proc_init
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5.4. Executing PROC_INIT pass (extract init attributes).
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yosys> proc_arst
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5.5. Executing PROC_ARST pass (detect async resets in processes).
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yosys> proc_rom
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5.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~2 debug messages>
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yosys> proc_mux
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5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\control.$proc$example.v:43$1'.
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1/2: $0\addr[7:0]
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2/2: $0\state[1:0]
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yosys> proc_dlatch
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5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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yosys> proc_dff
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5.9. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\control.\state' using process `\control.$proc$example.v:43$1'.
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created $dff cell `$procdff$12' with positive edge clock.
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Creating register for signal `\control.\addr' using process `\control.$proc$example.v:43$1'.
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created $dff cell `$procdff$13' with positive edge clock.
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yosys> proc_memwr
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5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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yosys> proc_clean
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5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Found and cleaned up 2 empty switches in `\control.$proc$example.v:43$1'.
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Removing empty process `control.$proc$example.v:43$1'.
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Cleaned up 2 empty switches.
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yosys> opt_expr -keepdc
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5.12. Executing OPT_EXPR pass (perform const folding).
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Optimizing module control.
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yosys> show -notitle -format dot -prefix control_proc
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6. Generating Graphviz representation of design.
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Writing dot description to `control_proc.dot'.
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Dumping module control to page 1.
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yosys> design -reset
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yosys> read_verilog example.v
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7. Executing Verilog-2005 frontend: example.v
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Parsing Verilog input from `example.v' to AST representation.
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Generating RTLIL representation for module `\example'.
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Generating RTLIL representation for module `\control'.
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Generating RTLIL representation for module `\data'.
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Successfully finished Verilog frontend.
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yosys> hierarchy -check -top example
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8. Executing HIERARCHY pass (managing design hierarchy).
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8.1. Analyzing design hierarchy..
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Top module: \example
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Used module: \data
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Used module: \control
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8.2. Analyzing design hierarchy..
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Top module: \example
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Used module: \data
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Used module: \control
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Removed 0 unused modules.
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yosys> show -notitle -format dot -prefix example_hier example
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9. Generating Graphviz representation of design.
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Writing dot description to `example_hier.dot'.
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Dumping module example to page 1.
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End of script. Logfile hash: b45465606c, CPU: user 0.01s system 0.00s, MEM: 11.86 MB peak
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Yosys 0.35+39 (git sha1 0cd4a10c8, clang 10.0.0-4ubuntu1 -fPIC -Os)
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Time spent: 37% 4x read_verilog (0 sec), 23% 3x show (0 sec), ...
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@ -1,76 +0,0 @@
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module example (
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input clk,
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input rst,
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input inc,
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input [7:0] a,
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input [7:0] b,
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output [15:0] c
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);
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wire [1:0] state;
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wire [7:0] addr;
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control ctrl (
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.clk(clk),
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.rst(rst),
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.inc(inc),
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.addr_o(addr),
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.state_o(state)
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);
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data dat (
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.clk(clk),
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.addr_i(addr),
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.state_i(state),
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.a(a),
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.b(b),
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.c(c)
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);
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endmodule
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module control (
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input clk,
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input rst,
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input inc,
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output [7:0] addr_o,
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output [1:0] state_o
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);
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reg [1:0] state;
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reg [7:0] addr;
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always @(posedge clk) begin
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if (rst) begin
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state <= 2'b00;
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addr <= 0;
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end else begin
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if (inc) state <= state + 1'b1;
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addr <= addr + 1'b1;
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end
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end
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endmodule //control
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module data (
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input clk,
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input [7:0] addr_i,
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input [1:0] state_i,
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input [7:0] a,
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input [7:0] b,
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output reg [15:0] c
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);
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reg [15:0] mem[255:0];
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always @(posedge clk) begin
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case (state_i)
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2'b00: mem[addr_i] <= a*b;
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2'b01: mem[addr_i] <= a+b;
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2'b10: mem[addr_i] <= a-b;
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2'b11: mem[addr_i] <= addr_i;
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endcase
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c <= mem[addr_i];
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end
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endmodule //data
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# turn command echoes on to use the log output as a console session
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echo on
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# ========================================================
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read_verilog -defer example.v
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hierarchy -top control
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show -notitle -format dot -prefix control_hier
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# ========================================================
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proc
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show -notitle -format dot -prefix control_proc
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# ========================================================
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design -reset
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read_verilog example.v
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hierarchy -check -top example
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show -notitle -format dot -prefix example_hier example
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16
docs/source/code_examples/fifo/Makefile
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16
docs/source/code_examples/fifo/Makefile
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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DOTS = addr_gen_hier.dot addr_gen_proc.dot
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DOTS += rdata_proc.dot rdata_flat.dot
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DOTS += fifo_flat.dot fifo_synth.dot
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dots: $(DOTS) fifo.out
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$(DOTS) fifo.out: fifo.v fifo.ys
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$(YOSYS) fifo.ys -l fifo.out -Q
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.PHONY: clean
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clean:
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rm -f *.dot
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2331
docs/source/code_examples/fifo/fifo.out
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2331
docs/source/code_examples/fifo/fifo.out
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File diff suppressed because it is too large
Load diff
73
docs/source/code_examples/fifo/fifo.v
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73
docs/source/code_examples/fifo/fifo.v
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// address generator/counter
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module addr_gen
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#( parameter MAX_DATA=256
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) ( input en, clk, rst,
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output reg [AWIDTH-1:0] addr
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);
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localparam AWIDTH = $clog2(MAX_DATA);
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initial addr <= 0;
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// async reset
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// increment address when enabled
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always @(posedge clk or posedge rst)
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if (rst)
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addr <= 0;
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else if (en) begin
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if (addr == MAX_DATA-1)
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addr <= 0;
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else
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addr <= addr + 1;
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end
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endmodule //addr_gen
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// Define our top level fifo entity
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module fifo
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#( parameter MAX_DATA=256
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) ( input wen, ren, clk, rst,
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input [7:0] wdata,
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output reg [7:0] rdata,
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output reg [AWIDTH:0] count
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);
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localparam AWIDTH = $clog2(MAX_DATA);
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// fifo storage
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// sync read before write
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wire [AWIDTH-1:0] waddr, raddr;
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reg [7:0] data [MAX_DATA-1:0];
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always @(posedge clk) begin
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if (wen)
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data[waddr] <= wdata;
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rdata <= data[raddr];
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end // storage
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// addr_gen for both write and read addresses
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addr_gen #(.MAX_DATA(MAX_DATA))
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fifo_writer (
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.en (wen),
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.clk (clk),
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.rst (rst),
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.addr (waddr)
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);
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addr_gen #(.MAX_DATA(MAX_DATA))
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fifo_reader (
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.en (ren),
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.clk (clk),
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.rst (rst),
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.addr (raddr)
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);
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// status signals
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initial count <= 0;
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always @(posedge clk or posedge rst) begin
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if (rst)
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count <= 0;
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else if (wen && !ren)
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count <= count + 1;
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else if (ren && !wen)
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count <= count - 1;
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end
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endmodule
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39
docs/source/code_examples/fifo/fifo.ys
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39
docs/source/code_examples/fifo/fifo.ys
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# ========================================================
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# throw in some extra text to match what we expect if we were opening an
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# interactive terminal
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log $ yosys fifo.v
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log
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log -- Parsing `fifo.v' using frontend ` -vlog2k' --
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read_verilog -defer fifo.v
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# turn command echoes on to use the log output as a console session
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echo on
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hierarchy -top addr_gen
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show -notitle -format dot -prefix addr_gen_hier
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# ========================================================
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proc
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show -notitle -format dot -prefix addr_gen_proc
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# ========================================================
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design -reset
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read_verilog fifo.v
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hierarchy -check -top fifo
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proc
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show -notitle -format dot -prefix rdata_proc o:rdata %ci*
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# ========================================================
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flatten
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show -notitle -format dot -prefix rdata_flat o:rdata %ci*
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# ========================================================
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opt_clean
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show -notitle -format dot -prefix fifo_flat
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design -reset
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read_verilog fifo.v
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synth_ice40 -dsp -top fifo
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show -notitle -format dot -prefix fifo_synth
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stat
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