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yosys/docs/source/code_examples/example_synth/example.ys
Krystine Sherwin 80c78aaad6
New example_synth code
`example_synth.rst` updated down to coarse-grain representation.
2023-12-14 16:21:52 +13:00

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# turn command echoes on to use the log output as a console session
echo on
# ========================================================
read_verilog -defer example.v
hierarchy -top control
show -notitle -format dot -prefix control_hier
# ========================================================
proc
show -notitle -format dot -prefix control_proc
# ========================================================
design -reset
read_verilog example.v
hierarchy -check -top example
show -notitle -format dot -prefix example_hier example