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yosys/docs/source/code_examples/fifo/Makefile
Krystine Sherwin 742ec78ca3
Switching example synth to fifo
Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
2023-12-18 13:19:01 +13:00

17 lines
308 B
Makefile

PROGRAM_PREFIX :=
YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
DOTS = addr_gen_hier.dot addr_gen_proc.dot
DOTS += rdata_proc.dot rdata_flat.dot
DOTS += fifo_flat.dot fifo_synth.dot
dots: $(DOTS) fifo.out
$(DOTS) fifo.out: fifo.v fifo.ys
$(YOSYS) fifo.ys -l fifo.out -Q
.PHONY: clean
clean:
rm -f *.dot