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77 lines
1,002 B
Verilog
77 lines
1,002 B
Verilog
module example (
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input clk,
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input rst,
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input inc,
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input [7:0] a,
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input [7:0] b,
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output [15:0] c
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);
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wire [1:0] state;
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wire [7:0] addr;
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control ctrl (
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.clk(clk),
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.rst(rst),
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.inc(inc),
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.addr_o(addr),
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.state_o(state)
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);
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data dat (
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.clk(clk),
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.addr_i(addr),
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.state_i(state),
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.a(a),
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.b(b),
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.c(c)
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);
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endmodule
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module control (
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input clk,
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input rst,
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input inc,
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output [7:0] addr_o,
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output [1:0] state_o
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);
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reg [1:0] state;
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reg [7:0] addr;
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always @(posedge clk) begin
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if (rst) begin
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state <= 2'b00;
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addr <= 0;
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end else begin
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if (inc) state <= state + 1'b1;
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addr <= addr + 1'b1;
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end
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end
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endmodule //control
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module data (
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input clk,
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input [7:0] addr_i,
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input [1:0] state_i,
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input [7:0] a,
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input [7:0] b,
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output reg [15:0] c
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);
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reg [15:0] mem[255:0];
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always @(posedge clk) begin
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case (state_i)
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2'b00: mem[addr_i] <= a*b;
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2'b01: mem[addr_i] <= a+b;
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2'b10: mem[addr_i] <= a-b;
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2'b11: mem[addr_i] <= addr_i;
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endcase
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c <= mem[addr_i];
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end
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endmodule //data
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