mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-14 12:58:45 +00:00
148 lines
4.3 KiB
Plaintext
148 lines
4.3 KiB
Plaintext
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-- Executing script file `example.ys' --
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echo on
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yosys> read_verilog -defer example.v
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1. Executing Verilog-2005 frontend: example.v
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Parsing Verilog input from `example.v' to AST representation.
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Storing AST representation for module `$abstract\example'.
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Storing AST representation for module `$abstract\control'.
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Storing AST representation for module `$abstract\data'.
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Successfully finished Verilog frontend.
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yosys> hierarchy -top control
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2. Executing HIERARCHY pass (managing design hierarchy).
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3. Executing AST frontend in derive mode using pre-parsed AST for module `\control'.
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Generating RTLIL representation for module `\control'.
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3.1. Analyzing design hierarchy..
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Top module: \control
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3.2. Analyzing design hierarchy..
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Top module: \control
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Removing unused module `$abstract\data'.
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Removing unused module `$abstract\control'.
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Removing unused module `$abstract\example'.
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Removed 3 unused modules.
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yosys> show -notitle -format dot -prefix control_hier
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4. Generating Graphviz representation of design.
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Writing dot description to `control_hier.dot'.
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Dumping module control to page 1.
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yosys> proc
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5. Executing PROC pass (convert processes to netlists).
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yosys> proc_clean
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5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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yosys> proc_rmdead
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5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$example.v:43$1 in module control.
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Removed a total of 0 dead cases.
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yosys> proc_prune
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5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 1 redundant assignment.
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Promoted 0 assignments to connections.
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yosys> proc_init
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5.4. Executing PROC_INIT pass (extract init attributes).
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yosys> proc_arst
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5.5. Executing PROC_ARST pass (detect async resets in processes).
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yosys> proc_rom
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5.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~2 debug messages>
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yosys> proc_mux
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5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\control.$proc$example.v:43$1'.
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1/2: $0\addr[7:0]
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2/2: $0\state[1:0]
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yosys> proc_dlatch
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5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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yosys> proc_dff
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5.9. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\control.\state' using process `\control.$proc$example.v:43$1'.
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created $dff cell `$procdff$12' with positive edge clock.
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Creating register for signal `\control.\addr' using process `\control.$proc$example.v:43$1'.
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created $dff cell `$procdff$13' with positive edge clock.
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yosys> proc_memwr
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5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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yosys> proc_clean
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5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Found and cleaned up 2 empty switches in `\control.$proc$example.v:43$1'.
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Removing empty process `control.$proc$example.v:43$1'.
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Cleaned up 2 empty switches.
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yosys> opt_expr -keepdc
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5.12. Executing OPT_EXPR pass (perform const folding).
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Optimizing module control.
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yosys> show -notitle -format dot -prefix control_proc
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6. Generating Graphviz representation of design.
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Writing dot description to `control_proc.dot'.
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Dumping module control to page 1.
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yosys> design -reset
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yosys> read_verilog example.v
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7. Executing Verilog-2005 frontend: example.v
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Parsing Verilog input from `example.v' to AST representation.
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Generating RTLIL representation for module `\example'.
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Generating RTLIL representation for module `\control'.
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Generating RTLIL representation for module `\data'.
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Successfully finished Verilog frontend.
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yosys> hierarchy -check -top example
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8. Executing HIERARCHY pass (managing design hierarchy).
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8.1. Analyzing design hierarchy..
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Top module: \example
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Used module: \data
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Used module: \control
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8.2. Analyzing design hierarchy..
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Top module: \example
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Used module: \data
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Used module: \control
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Removed 0 unused modules.
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yosys> show -notitle -format dot -prefix example_hier example
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9. Generating Graphviz representation of design.
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Writing dot description to `example_hier.dot'.
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Dumping module example to page 1.
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End of script. Logfile hash: b45465606c, CPU: user 0.01s system 0.00s, MEM: 11.86 MB peak
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Yosys 0.35+39 (git sha1 0cd4a10c8, clang 10.0.0-4ubuntu1 -fPIC -Os)
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Time spent: 37% 4x read_verilog (0 sec), 23% 3x show (0 sec), ...
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