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https://github.com/YosysHQ/yosys
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742ec78ca3
Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
40 lines
1 KiB
Plaintext
40 lines
1 KiB
Plaintext
# ========================================================
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# throw in some extra text to match what we expect if we were opening an
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# interactive terminal
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log $ yosys fifo.v
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log
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log -- Parsing `fifo.v' using frontend ` -vlog2k' --
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read_verilog -defer fifo.v
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# turn command echoes on to use the log output as a console session
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echo on
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hierarchy -top addr_gen
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show -notitle -format dot -prefix addr_gen_hier
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# ========================================================
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proc
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show -notitle -format dot -prefix addr_gen_proc
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# ========================================================
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design -reset
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read_verilog fifo.v
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hierarchy -check -top fifo
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proc
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show -notitle -format dot -prefix rdata_proc o:rdata %ci*
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# ========================================================
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flatten
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show -notitle -format dot -prefix rdata_flat o:rdata %ci*
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# ========================================================
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opt_clean
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show -notitle -format dot -prefix fifo_flat
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design -reset
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read_verilog fifo.v
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synth_ice40 -dsp -top fifo
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show -notitle -format dot -prefix fifo_synth
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stat
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