fpga support and arty a7 100t #38

Merged

programmerjake merged 20 commits from programmerjake/fayalite:fpga-support-and-arty-a7-100t into master

2025-10-22 05:36:13 +00:00

Author	SHA1	Message	Date
Jacob Lifshay	c6feea6d51	properly handle all `XilinxAnnotation`s, this makes nextpnr-xilinx properly pick up the clock frequency All checks were successful / test (pull_request) Successful in 4m34s Details / test (push) Successful in 5m9s Details	2025-10-21 22:24:02 -07:00
Jacob Lifshay	409992961c	switch to using verilog for reset synchronizer so we can use attributes on FDPE instances	2025-10-21 22:24:02 -07:00
Jacob Lifshay	2bdc8a7c72	WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it All checks were successful / test (pull_request) Successful in 4m35s Details	2025-10-19 23:13:28 -07:00
Jacob Lifshay	477a1f2d29	Add peripherals and Arty A7 platforms -- blinky works correctly now on arty-a7-100t!	2025-10-19 23:13:28 -07:00
Jacob Lifshay	4d54f903be	move vendor module to top level	2025-10-17 15:00:19 -07:00
Jacob Lifshay	3f5dd61e46	WIP adding Platform All checks were successful / test (pull_request) Successful in 4m28s Details	2025-10-17 05:55:22 -07:00
Jacob Lifshay	def406ab52	group all xilinx annotations together All checks were successful / test (pull_request) Successful in 4m23s Details	2025-10-16 04:53:58 -07:00
Jacob Lifshay	a565be1b09	do some clean up All checks were successful / test (pull_request) Successful in 4m24s Details	2025-10-16 04:32:56 -07:00
Jacob Lifshay	676c1e3b7d	WIP adding annotations for generating the .xdc file for yosys-nextpnr-prjxray All checks were successful / test (pull_request) Successful in 4m27s Details	2025-10-15 04:29:00 -07:00
Jacob Lifshay	169be960f8	generate Arty A7 100T .bit file for blinky example in CI	2025-10-15 04:29:00 -07:00
Jacob Lifshay	2b52799f5c	try building .bit file	2025-10-15 04:29:00 -07:00
Jacob Lifshay	35f98f3229	fix redirects	2025-10-15 04:29:00 -07:00
Jacob Lifshay	8a63ea89d0	WIP adding yosys-nextpnr-xray xilinx fpga toolchain -- blinky works on arty a7 100t (except for inverted reset)	2025-10-15 04:29:00 -07:00
Jacob Lifshay	84c5978eaf	WIP build Xilinx FPGA dependencies in CI	2025-10-15 04:29:00 -07:00
Jacob Lifshay	42e3179a60	change cache directory name to be fayalite-specific	2025-10-15 04:29:00 -07:00
Jacob Lifshay	53ae3ff670	mark create-unix-shell-script as incomplete in CLI	2025-10-15 04:29:00 -07:00
Jacob Lifshay	7af9abfb6f	switch to using new crate::build system	2025-10-15 04:29:00 -07:00
Jacob Lifshay	aacd05378f	WIP converting from cli.rs to build/*.rs	2025-10-15 04:29:00 -07:00
Jacob Lifshay	908ccef674	added automatically-added dependencies; added caching for external jobs	2025-10-15 04:29:00 -07:00
Jacob Lifshay	057670c12a	WIP adding FPGA support -- build module should be complete	2025-10-15 04:29:00 -07:00