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NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain). #4

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opened 2025-08-26 06:25:23 +00:00 by programmerjake · 1 comment
programmerjake commented 2025-08-26 06:25:23 +00:00
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Issue for tracking progress of a subtask of NLnet grant 2024-12-324:
Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).

Issue for tracking progress of a subtask of [NLnet grant 2024-12-324](https://git.libre-chip.org/libre-chip/grant-tracking/src/branch/master/nlnet-2024-12-324/progress.md): Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain). <!-- add additional content here if you like -->
programmerjake added this to the NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs project 2025-08-26 06:25:23 +00:00
programmerjake self-assigned this 2025-09-10 10:16:14 +00:00
programmerjake commented 2025-10-22 06:15:57 +00:00
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"Results" from request for payment for this and #6, since it's probably useful for others:

I rewrote the code for Fayalite's CLI to support being extensible from outside the Fayalite library, as well as to have a graph-based build process. I then added support for using yosys, nextpnr-xilinx, and prjxray to build FPGA bitstreams for selected Xilinx 7-series FPGAs. I also added an API for making it much easier to use peripherals from the selected FPGA board, for now it just includes the clock, reset, and LEDs on the Arty A7 boards.

Main PR:
libre-chip/fayalite#38

New repo that builds podman/docker container images with all the external dependencies needed (though I tried to make Fayalite work fine if you built those dependencies yourself instead of using the container image):
https://git.libre-chip.org/libre-chip/fayalite-deps

I also added docs for building the Blinky example for the Arty A7 100T:
libre-chip/fayalite#40

"Results" from request for payment for this and #6, since it's probably useful for others: I rewrote the code for Fayalite's CLI to support being extensible from outside the Fayalite library, as well as to have a graph-based build process. I then added support for using yosys, nextpnr-xilinx, and prjxray to build FPGA bitstreams for selected Xilinx 7-series FPGAs. I also added an API for making it much easier to use peripherals from the selected FPGA board, for now it just includes the clock, reset, and LEDs on the Arty A7 boards. Main PR: https://git.libre-chip.org/libre-chip/fayalite/pulls/38 New repo that builds podman/docker container images with all the external dependencies needed (though I tried to make Fayalite work fine if you built those dependencies yourself instead of using the container image): https://git.libre-chip.org/libre-chip/fayalite-deps I also added docs for building the Blinky example for the Arty A7 100T: https://git.libre-chip.org/libre-chip/fayalite/pulls/40
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#5 NLnet 2024-12-324 Add support for the Orange Crab since both Cesar and Jacob have one.
libre-chip/grant-tracking
#6 NLnet 2024-12-324 Add support for the Arty A7 100T since that's what we're using for CI.
libre-chip/grant-tracking
Reference: libre-chip/grant-tracking#4
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