91e1b619e8
switch to petgraph 0.8.1 now that my PR was merged and released to crates.io
/ deps (pull_request) Successful in 18s
/ test (pull_request) Successful in 4m25s
2025-04-09 20:48:40 -07:00
e2d2d4110b
upgrade hashbrown to 0.15.2
2025-04-09 20:33:21 -07:00
b1f9706e4e
add custom hasher for testing
2025-04-09 20:27:22 -07:00
4eda4366c8
check types in debug mode in impl Debug for Expr, helping to catch bugs
2025-04-09 20:23:19 -07:00
122c08d3cf
add fake which for miri
2025-04-09 20:21:43 -07:00
b08a747e20
switch to using type aliases for HashMap/HashSet to allow easily switching hashers
2025-04-09 20:17:46 -07:00
e0c9939147
add test that SimValue can't be interned, since its PartialEq may ignore types
2025-04-09 19:55:09 -07:00
07725ab489
switch interning to use HashTable rather than HashMap
2025-04-09 19:30:02 -07:00
36f1b9bbb6
add derive(Debug) to all types that are interned
2025-04-09 19:24:08 -07:00
9a1b047d2f
change TypeIdMap to not use any unsafe code
2025-04-09 16:25:56 -07:00
5967e812a2
fix [SU]IntValue's PartialEq for interning
...
/ deps (pull_request) Successful in 17s
/ test (pull_request) Successful in 4m23s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m52s
different widths must make values compare not equal otherwise interning
will e.g. substitute a 0x0_u8 for a 0x0_u2
2025-04-08 21:57:56 -07:00
001fd31451
add UIntInRange[Inclusive][Type]
/ deps (pull_request) Successful in 18s
/ test (pull_request) Successful in 4m21s
/ deps (push) Successful in 13s
/ test (push) Successful in 5m7s
2025-04-07 18:27:54 -07:00
57aae7b7fb
implement [de]serializing BaseTypes, SimValues, and support PhantomConst<T> in #[hdl] struct S<T>
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m16s
/ deps (push) Successful in 12s
/ test (push) Successful in 4m46s
2025-04-04 01:04:26 -07:00
6929352be7
re-export bitvec and add types useful for simulation to the prelude
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m12s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m40s
2025-04-03 16:01:39 -07:00
62058dc141
fix cargo doc warnings -- convert urls to auto links
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 4m19s
/ deps (push) Successful in 13s
/ test (push) Successful in 5m7s
2025-04-01 22:22:54 -07:00
c4b6a0fee6
add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m16s
2025-04-01 22:16:47 -07:00
9092e45447
fix #[hdl(sim)] match on enums
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m12s
2025-03-30 01:25:07 -07:00
a40eaaa2da
expand SimValue support
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 4m11s
2025-03-30 00:55:38 -07:00
5028401a5a
change SimValue to contain and deref to a value and not just contain bits
2025-03-27 23:44:36 -07:00
e0f978fbb6
silence unused m variable warning in #[hdl_module] with an empty body.
2025-03-27 23:17:28 -07:00
ec3a61513b
simulator read/write types must be passive
2025-03-27 23:03:44 -07:00
fdc73b5f3b
add ripple counter test to test simulating alternating circuits and extern modules
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m19s
/ deps (push) Successful in 12s
/ test (push) Successful in 4m26s
2025-03-25 18:56:26 -07:00
a115585d5a
simulator: allow external module generators to wait for value changes and/or clock edges
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 4m2s
2025-03-25 18:26:48 -07:00
ab9ff4f2db
simplify setting an extern module simulation
/ deps (pull_request) Successful in 12m46s
/ test (pull_request) Successful in 4m8s
2025-03-21 17:08:29 -07:00
d1bd176b28
implement simulation of extern modules
/ deps (pull_request) Successful in 11m39s
/ test (pull_request) Successful in 3m55s
2025-03-21 01:47:14 -07:00
920d8d875f
add some missing #[track_caller]
2025-03-19 17:10:51 -07:00
d453755bb2
add ExprPartialEq/ExprPartialOrd impls for PhantomConst
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m45s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m10s
2025-03-10 19:40:03 -07:00
450e1004b6
fix using fayalite as a dependency
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 3m51s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m14s
2025-03-09 23:14:14 -07:00
c0c5b550bc
add PhantomConst
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m51s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m15s
2025-03-09 21:03:47 -07:00
2fa0ea6192
make FillInDefaultedGenerics work with Sizes and not just Types
2025-03-09 20:59:21 -07:00
bd75fdfefd
add efficient prefix-sums and reductions
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m40s
/ deps (push) Successful in 14s
/ test (push) Successful in 4m5s
2025-03-02 23:04:17 -08:00
50c86e18dc
add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T>
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 3m40s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m5s
2025-03-02 18:02:34 -08:00
60734cc9d1
switch CI to use mirrors
/ deps (pull_request) Successful in 12m27s
/ test (pull_request) Successful in 4m3s
/ deps (push) Successful in 14s
/ test (push) Successful in 4m14s
2025-03-02 17:43:29 -08:00
3458c21f44
add #[hdl(cmp_eq)] to implement HdlPartialEq automatically
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m38s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m10s
2025-02-16 20:48:16 -08:00
43797db36e
sort custom keywords
2025-02-16 20:46:54 -08:00
cdd84953d0
support unknown trait bounds in type parameters
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m34s
/ deps (push) Successful in 14s
/ test (push) Successful in 3m58s
2025-02-13 18:35:30 -08:00
86a1bb46be
add #[hdl] let destructuring and, while at it, tuple patterns
/ deps (pull_request) Successful in 11m32s
/ test (pull_request) Successful in 3m44s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m9s
2025-02-10 22:49:41 -08:00
209d5b5fe1
fix broken doc links
2025-02-10 22:49:16 -08:00
d4ea826051
sim: fix "label address not set" bug when the last Assignment is conditional
/ deps (pull_request) Successful in 23s
/ test (pull_request) Successful in 3m32s
/ deps (push) Successful in 15s
/ test (push) Successful in 3m58s
2025-01-15 19:04:40 -08:00
404a2ee043
tests/sim: add test_array_rw
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m34s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m2s
2025-01-12 21:38:59 -08:00
e3a2ccd41c
properly handle duplicate names in vcd
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 3m43s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m8s
2025-01-09 22:52:22 -08:00
3771cea78e
Gather the FIFO debug ports in a bundle
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m35s
/ deps (push) Successful in 16s
/ test (push) Successful in 3m59s
2024-12-29 13:17:24 -03:00
dcf865caec
Add assertions and debug ports in order for the FIFO to pass induction
...
As some proofs involving memories, it is necessary to add more ports to
the queue interface, to sync state. These changes are predicated on the
test environment, so normal use is not affected.
Since some speedup is achieved, use the saved time to test with a deeper
FIFO.
2024-12-29 13:12:58 -03:00
31d01046a8
Initial queue formal proof based on one-entry FIFO equivalence
...
For now, only check that the basic properties work in bounded model check
mode, leave the induction proof for later.
Partially replace the previously existing proof.
Remove earlier assumptions and bounds that don't apply for this proof.
Use parameterized types instead of hard-coded types.
2024-12-29 13:04:01 -03:00
c16726cee6
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
/ deps (pull_request) Successful in 17s
/ test (pull_request) Successful in 5m13s
/ deps (push) Successful in 14s
/ test (push) Successful in 5m42s
2024-12-29 00:48:15 -08:00
b63676d0ca
add test for cfgs
/ deps (pull_request) Successful in 18s
/ test (pull_request) Successful in 5m23s
/ deps (push) Successful in 14s
/ test (push) Successful in 6m5s
2024-12-28 23:39:50 -08:00
7005fa3330
implement handling #[cfg] and #[cfg_attr] in proc macro inputs
2024-12-28 23:39:08 -08:00
2ab8428062
upgrade syn version
2024-12-28 23:39:08 -08:00
9b06019bf5
make sim::Compiler not print things to stdout unless you ask for it
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 5m12s
/ deps (push) Successful in 16s
/ test (push) Successful in 5m18s
2024-12-18 21:15:09 -08:00
36bad52978
sim: fix sim.write to struct
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 5m16s
/ deps (push) Successful in 14s
/ test (push) Successful in 5m14s
2024-12-18 20:50:50 -08:00
