properly handle duplicate names in vcd
test.yml #223 -Commit
e3a2ccd41c
pushed by
programmerjake
properly handle duplicate names in vcd
test.yml #222 -Commit
e3a2ccd41c
pushed by
programmerjake
Gather the FIFO debug ports in a bundle
test.yml #221 -Commit
3771cea78e
pushed by
programmerjake
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
test.yml #218 -Commit
c16726cee6
pushed by
programmerjake
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
test.yml #217 -Commit
c16726cee6
pushed by
programmerjake
Add assertions and debug ports in order for the FIFO to pass induction
test.yml #210 -Commit
ad1101934c
pushed by
cesar
Initial queue formal proof based on one-entry FIFO equivalence
test.yml #209 -Commit
fef7fea3ea
pushed by
cesar
make sim::Compiler not print things to stdout unless you ask for it
test.yml #208 -Commit
9b06019bf5
pushed by
programmerjake
make sim::Compiler not print things to stdout unless you ask for it
test.yml #207 -Commit
9b06019bf5
pushed by
programmerjake
sim: add SimValue and reading/writing more than just a scalar
test.yml #203 -Commit
21c73051ec
pushed by
programmerjake
sim: add SimValue and reading/writing more than just a scalar
test.yml #202 -Commit
21c73051ec
pushed by
programmerjake
sim: add SimValue and reading/writing more than just a scalar
test.yml #201 -Commit
21c73051ec
pushed by
programmerjake
Merge remote-tracking branch 'origin/master' into adding-simulator
test.yml #200 -Commit
304d8da0e8
pushed by
programmerjake
Merge remote-tracking branch 'origin/master' into adding-simulator
test.yml #199 -Commit
304d8da0e8
pushed by
programmerjake
Merge remote-tracking branch 'origin/master' into adding-simulator
test.yml #198 -Commit
304d8da0e8
pushed by
programmerjake
tests/sim: add test for memory rw port
test.yml #194 -Commit
c756aeec70
pushed by
programmerjake
sim: simple memory test works!
test.yml #192 -Commit
903ca1bf30
pushed by
programmerjake