writing VCD for combinatorial circuits works!
test.yml #129 -Commit
e2653a3245
pushed by
programmerjake
writing VCD for combinatorial circuits works!
test.yml #128 -Commit
e2653a3245
pushed by
programmerjake
Add test module exercising formal verification.
test.yml #127 -Commit
c1f1a8b749
pushed by
programmerjake
wire up simulator trace writing interface
test.yml #122 -Commit
904752fa0c
pushed by
programmerjake
simple combinatorial simulation works!
test.yml #120 -Commit
414a2d74f1
pushed by
programmerjake
Simulation::settle_step() works for simple modules
test.yml #119 -Commit
2e9d5c1835
pushed by
programmerjake
simulator WIP: use petgraph for topological sort over assignments
test.yml #118 -Commit
d7d8e2e7ce
pushed by
programmerjake
add missing copyright headers
test.yml #114 -Commit
41ce9b3474
pushed by
programmerjake
split out deps into separate workflow with better caching using deps.yml from cpu.git
test.yml #109 -Commit
0c9c48a066
pushed by
programmerjake
split out deps into separate workflow with better caching using deps.yml from cpu.git
test.yml #108 -Commit
0c9c48a066
pushed by
programmerjake
limit sby to one thread each since it seems not to respect job count in parallel mode
test.yml #107 -Commit
cb17913004
pushed by
programmerjake
formal: add workaround for wires disappearing because yosys optimizes them out
test.yml #105 -Commit
3d0f95cfe5
pushed by
programmerjake
get #[hdl] struct S<A: KnownSize, B: KnownSize> to work
test.yml #103 -Commit
d0229fbcfb
pushed by
programmerjake
add more thorough checks that bounds are properly handled on #[hdl] structs
test.yml #102 -Commit
4909724995
pushed by
programmerjake
silence warnings for field names that start with _
test.yml #100 -Commit
1a2149b040
pushed by
programmerjake