add PowerISA decoder #7

Merged

programmerjake merged 35 commits from programmerjake/cpu:add-powerisa-decoder into master 2026-01-29 02:22:14 +00:00

Conversation 1 Commits 35 Files changed 31 +215042 -36165

programmerjake commented 2026-01-19 06:53:43 +00:00

Owner

Copy link

Fixes: libre-chip/grant-tracking#12

Fixes: https://git.libre-chip.org/libre-chip/grant-tracking/issues/12

programmerjake added 8 commits 2026-01-19 06:53:43 +00:00

rename src/powerisa.rs -> src/powerisa_instructions_xml.rs 305d7b0ae6

WIP adding simple power isa decoder 6d40eaadb3

decodes an addi instruction b7b6a02777

decode some more add instructions 62512960c3

decode all fixed-point add/sub instructions other than addex a4b052f5f3

decode fixed-point compare instructions 3a35a698e2

decode bitwise logic instructions; also nop and mr special cases 7ebcd5de1e

add test that UnitMOp has all the register fields aligned across the different variants c9a3de19b7

programmerjake added 1 commit 2026-01-19 07:24:12 +00:00

update reg_alloc.vcd 62a330ed4d

programmerjake added 3 commits 2026-01-20 04:10:21 +00:00

simplify tests/simple_power_isa_decoder::test_cases somewhat aa85ecab01

decode exts[bhw][.] and pnop 1fc56e02f9

add branch instructions, no tests yet 2e05329c36

programmerjake added 1 commit 2026-01-20 06:39:39 +00:00

add tests for and fix decoding branch instructions 85ada6e55a

programmerjake added 2 commits 2026-01-21 00:20:59 +00:00

extract lut out into separate Lut4 type and add test a93dca25ac

mark .vcd files as generated 0433e4f8f1

programmerjake added 2 commits 2026-01-22 15:35:20 +00:00

refactor PRegFlags to use view structs instead of a long list of accessor methods ffc3d4283c

implement decoding mcrxrx 9b8d99e9af

programmerjake added 1 commit 2026-01-22 16:29:24 +00:00

fix & clean up MOp definitions and ensure_reg_fields_are_in_the_same_place e6f876f9af

programmerjake added 5 commits 2026-01-23 19:47:26 +00:00

move simple_power_isa_decoder integration test into its own folder 87112c681a

split up tests/simple_power_isa_decoder into separate modules fc8a6cd959

reorder the decoder test cases to match the PowerISA v3.1C PDF 5e9d0957f6

implement decoding condition register logical instructions 33529a2296

implement decoding mcrf 29757a568c

programmerjake added 2 commits 2026-01-23 20:13:21 +00:00

make check-copyright.sh also handle other tests/.../expected/... files aa07e24c78

make LogicalFlagsMOp also copy the dest PRegValue.flags into PRegValue.int_fp d361a2b578

programmerjake added 1 commit 2026-01-24 00:08:06 +00:00

implement decoding 8/16/32/64-bit load instructions -- all of Power ISA v3.1C Book I 3.3.2 706d54ae0d

programmerjake added 1 commit 2026-01-25 23:07:06 +00:00

implement decoding 8/16/32/64-bit store instructions -- all of Power ISA v3.1c Book I 3.3.3 0824b63d31

programmerjake added 2 commits 2026-01-26 04:35:18 +00:00

simplify getting IMM_WIDTH for LogicalFlagsMOpImm 2ad469e331

add shift/rotate MOp definition 59874b9b29

programmerjake added 2 commits 2026-01-27 00:13:45 +00:00

implement decoding shifts: s[lr][wd][.] and sra[wd][i][.] 1db65ae753

reduce the number of wires to have one per form/field pair instead of one per insn/field pair faa8dde774

programmerjake added 3 commits 2026-01-28 03:20:28 +00:00

implement decoding extswsli[.] 167bc4b6a6

change CommonMOp to directly contain a generic immediate type 130c1b2892

implement decoding all rotate instructions a42b76b468

programmerjake added 1 commit 2026-01-29 01:35:25 +00:00

implement decoding mtspr/mfspr/mftb f88346ea37

programmerjake changed title from WIP: add PowerISA decoder to add PowerISA decoder 2026-01-29 01:37:35 +00:00

programmerjake commented 2026-01-29 02:22:00 +00:00

Author

Owner

Copy link

The decoder handles decoding either 32 or 64-bit (prefixed) instructions, and for each instruction generates 0-3 µOps:

• no-ops decode to 0 µOps
• most instructions decode to 1 µOp
• loads and stores decode to 2 µOps
• branch-and-decrement-ctr instructions decode to 2 µOps
• store-update instructions with all register arguments being the same register need 3 µOps for:
  • calculate the address into a temporary
  • do the store
  • move from the temporary into the updated register.

I've implemented decoding most of the simple branch and integer instructions:

• b[l][a]
• bc[l][a]/bclr[l]/bcctr[l]/bctar[l]
• crand/crnand/cror/crxor/crnor/creqv/crandc/crorc
• mcrf
• lbz[u][x]/plbz
• lh[za][u][x]/plhz
• lw[za][u][x]/plwz
• ld[u][x]/pld
• stb[u][x]/pstb
• sth[u][x]/psth
• stw[u][x]/pstw
• std[u][x]/pstd
• addi/paddi
• addis
• addpcis
• add[o][.]
• addic[.]
• subf[o][.]
• subfic
• addc[o][.]
• subfc[o][.]
• adde[o][.]
• subfe[o][.]
• addme[o][.]/addze[o][.]/subfme[o][.]/subfze[o][.]
• neg[o][.]
• cmp[l][i]
• cmprb
• cmpeqb
• andi./andis./ori/oris/xori/xoris
• and[.]/xor[.]/nand[.]/or[.]/orc[.]/nor[.]/eqv[.]/andc[.]
• extsb[.]/extsh[.]/extsw[.]
• rlwinm[.]/rlwnm[.]/rlwimi[.]/rldicl[.]/rldicr[.]/rldic[.]/rldcl[.]/rldcr[.]/rldimi[.]
• slw[.]/srw[.]/srawi[.]/sraw[.]/sld[.]/sradi[.]/srd[.]/srad[.]
• extswsli[.]
• mtspr/mfspr/mftb -- for LR, CTR, TAR, TB, and TBU.
• mcrxrx
• pnop

The decoder handles decoding either 32 or 64-bit (prefixed) instructions, and for each instruction generates 0-3 µOps: * no-ops decode to 0 µOps * most instructions decode to 1 µOp * loads and stores decode to 2 µOps * branch-and-decrement-ctr instructions decode to 2 µOps * store-update instructions with all register arguments being the same register need 3 µOps for: * calculate the address into a temporary * do the store * move from the temporary into the updated register. I've implemented decoding most of the simple branch and integer instructions: * `b[l][a]` * `bc[l][a]`/`bclr[l]`/`bcctr[l]`/`bctar[l]` * `crand`/`crnand`/`cror`/`crxor`/`crnor`/`creqv`/`crandc`/`crorc` * `mcrf` * `lbz[u][x]`/`plbz` * `lh[za][u][x]`/`plhz` * `lw[za][u][x]`/`plwz` * `ld[u][x]`/`pld` * `stb[u][x]`/`pstb` * `sth[u][x]`/`psth` * `stw[u][x]`/`pstw` * `std[u][x]`/`pstd` * `addi`/`paddi` * `addis` * `addpcis` * `add[o][.]` * `addic[.]` * `subf[o][.]` * `subfic` * `addc[o][.]` * `subfc[o][.]` * `adde[o][.]` * `subfe[o][.]` * `addme[o][.]`/`addze[o][.]`/`subfme[o][.]`/`subfze[o][.]` * `neg[o][.]` * `cmp[l][i]` * `cmprb` * `cmpeqb` * `andi.`/`andis.`/`ori`/`oris`/`xori`/`xoris` * `and[.]`/`xor[.]`/`nand[.]`/`or[.]`/`orc[.]`/`nor[.]`/`eqv[.]`/`andc[.]` * `extsb[.]`/`extsh[.]`/`extsw[.]` * `rlwinm[.]`/`rlwnm[.]`/`rlwimi[.]`/`rldicl[.]`/`rldicr[.]`/`rldic[.]`/`rldcl[.]`/`rldcr[.]`/`rldimi[.]` * `slw[.]`/`srw[.]`/`srawi[.]`/`sraw[.]`/`sld[.]`/`sradi[.]`/`srd[.]`/`srad[.]` * `extswsli[.]` * `mtspr`/`mfspr`/`mftb` -- for LR, CTR, TAR, TB, and TBU. * `mcrxrx` * `pnop`

programmerjake merged commit f88346ea37 into master 2026-01-29 02:22:14 +00:00

programmerjake deleted branch add-powerisa-decoder 2026-01-29 02:22:14 +00:00

programmerjake referenced this pull request from libre-chip/grant-tracking 2026-01-29 02:23:38 +00:00

NLnet 2024-12-324 Create the PowerISA decoder #12

Sign in to join this conversation.

Reviewers

No reviewers

Labels

Clear labels

No items

No labels

Milestone

Clear milestone

No items

No milestone

Projects

Clear projects

No items

No project

Assignees

Clear assignees

No assignees

1 participant

Notifications

Subscribe

Due date

The due date is invalid or out of range. Please use the format "yyyy-mm-dd".

No due date set.

Dependencies

No dependencies set.

Reference: libre-chip/cpu#7

No description provided.