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wip-splitting-reg-alloc

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• f88346ea37
  
  implement decoding mtspr/mfspr/mftb master Jacob Lifshay 2026-01-28 17:00:08 -08:00
• a42b76b468
  
  implement decoding all rotate instructions Jacob Lifshay 2026-01-26 21:42:22 -08:00
• 130c1b2892
  
  change CommonMOp to directly contain a generic immediate type Jacob Lifshay 2026-01-27 16:42:35 -08:00
• 167bc4b6a6
  
  implement decoding extswsli[.] Jacob Lifshay 2026-01-26 19:18:44 -08:00
• faa8dde774
  
  reduce the number of wires to have one per form/field pair instead of one per insn/field pair Jacob Lifshay 2026-01-26 16:11:03 -08:00
• 1db65ae753
  
  implement decoding shifts: s[lr][wd][.] and sra[wd][i][.] Jacob Lifshay 2026-01-26 15:14:26 -08:00
• 59874b9b29
  
  add shift/rotate MOp definition Jacob Lifshay 2026-01-25 20:34:38 -08:00
• 2ad469e331
  
  simplify getting IMM_WIDTH for LogicalFlagsMOpImm Jacob Lifshay 2026-01-25 20:25:25 -08:00
• 0824b63d31
  
  implement decoding 8/16/32/64-bit store instructions -- all of Power ISA v3.1c Book I 3.3.3 Jacob Lifshay 2026-01-25 15:06:14 -08:00
• 706d54ae0d
  
  implement decoding 8/16/32/64-bit load instructions -- all of Power ISA v3.1C Book I 3.3.2 Jacob Lifshay 2026-01-23 16:06:16 -08:00
• d361a2b578
  
  make LogicalFlagsMOp also copy the dest PRegValue.flags into PRegValue.int_fp Jacob Lifshay 2026-01-23 12:06:59 -08:00
• aa07e24c78
  
  make check-copyright.sh also handle other tests/.../expected/... files Jacob Lifshay 2026-01-23 12:11:49 -08:00
• 29757a568c
  
  implement decoding mcrf Jacob Lifshay 2026-01-23 11:47:06 -08:00
• 33529a2296
  
  implement decoding condition register logical instructions Jacob Lifshay 2026-01-23 11:27:48 -08:00
• 5e9d0957f6
  
  reorder the decoder test cases to match the PowerISA v3.1C PDF Jacob Lifshay 2026-01-23 09:46:29 -08:00
• fc8a6cd959
  
  split up tests/simple_power_isa_decoder into separate modules Jacob Lifshay 2026-01-23 09:38:45 -08:00
• 87112c681a
  
  move simple_power_isa_decoder integration test into its own folder Jacob Lifshay 2026-01-23 08:46:28 -08:00
• e6f876f9af
  
  fix & clean up MOp definitions and ensure_reg_fields_are_in_the_same_place Jacob Lifshay 2026-01-22 08:28:02 -08:00
• 9b8d99e9af
  
  implement decoding mcrxrx Jacob Lifshay 2026-01-21 02:14:35 -08:00
• ffc3d4283c
  
  refactor PRegFlags to use view structs instead of a long list of accessor methods Jacob Lifshay 2026-01-20 19:07:46 -08:00
• 0433e4f8f1
  
  mark .vcd files as generated Jacob Lifshay 2026-01-20 16:20:40 -08:00
• a93dca25ac
  
  extract lut out into separate Lut4 type and add test Jacob Lifshay 2026-01-20 16:03:28 -08:00
• 85ada6e55a
  
  add tests for and fix decoding branch instructions Jacob Lifshay 2026-01-19 22:38:48 -08:00
• 2e05329c36
  
  add branch instructions, no tests yet Jacob Lifshay 2026-01-19 17:19:38 -08:00
• 1fc56e02f9
  
  decode exts[bhw][.] and pnop Jacob Lifshay 2026-01-19 15:41:56 -08:00
• aa85ecab01
  
  simplify tests/simple_power_isa_decoder::test_cases somewhat Jacob Lifshay 2026-01-19 14:16:00 -08:00
• 62a330ed4d
  
  update reg_alloc.vcd Jacob Lifshay 2026-01-18 23:23:54 -08:00
• c9a3de19b7
  
  add test that UnitMOp has all the register fields aligned across the different variants Jacob Lifshay 2026-01-18 22:44:30 -08:00
• 7ebcd5de1e
  
  decode bitwise logic instructions; also nop and mr special cases Jacob Lifshay 2026-01-18 19:12:48 -08:00
• 3a35a698e2
  
  decode fixed-point compare instructions Jacob Lifshay 2026-01-18 16:37:00 -08:00
• a4b052f5f3
  
  decode all fixed-point add/sub instructions other than addex Jacob Lifshay 2026-01-18 15:02:15 -08:00
• 62512960c3
  
  decode some more add instructions Jacob Lifshay 2026-01-15 16:10:03 -08:00
• b7b6a02777
  
  decodes an addi instruction Jacob Lifshay 2026-01-14 21:41:25 -08:00
• 6d40eaadb3
  
  WIP adding simple power isa decoder Jacob Lifshay 2026-01-12 07:10:58 -08:00
• 305d7b0ae6
  
  rename src/powerisa.rs -> src/powerisa_instructions_xml.rs Jacob Lifshay 2026-01-12 03:31:06 -08:00
• 781dbc6bcb
  
  add copyright header to build.rs Jacob Lifshay 2026-01-09 02:05:08 -08:00
• 5faf0899a8
  
  fully parse powerisa-instructions.xml Jacob Lifshay 2026-01-09 02:03:59 -08:00
• 8c02483b65
  
  wip parsing the xml Jacob Lifshay 2026-01-08 00:09:20 -08:00
• e4a7d9f59c
  
  add build script that parses the PowerISA v3.1C pdf and produces an xml file Jacob Lifshay 2026-01-07 14:19:46 -08:00
• 3b5104c8fa
  
  fix vcd to match test output Jacob Lifshay 2025-12-16 23:25:54 -08:00
• 2de4a67360
  
  add link to other NLnet task and note lack of optimization Jacob Lifshay 2025-12-16 23:10:07 -08:00
• d5a7d9dd9e
  
  next_pc works afaict Jacob Lifshay 2025-12-16 23:06:32 -08:00
• 59da0aec06
  
  WIP fixing bugs Jacob Lifshay 2025-12-16 02:32:19 -08:00
• 5e1238b5c7
  
  replace tests/next_pc's demo program with a simple expression parser as a better demo Jacob Lifshay 2025-12-15 21:40:11 -08:00
• bc9a3a5ce7
  
  add missing copyright header and check-copyright.sh support for .mermaid Jacob Lifshay 2025-12-15 03:00:37 -08:00
• d42f010cda
  
  WIP fixing bugs Jacob Lifshay 2025-12-15 02:48:40 -08:00
• 84e4fde512
  
  fix queueing errors Jacob Lifshay 2025-12-15 00:47:53 -08:00
• 8ab63f3c6a
  
  update fayalite Jacob Lifshay 2025-12-14 21:05:59 -08:00
• f39f40ce1f
  
  fix next_pc::Queue and add test Jacob Lifshay 2025-12-14 20:39:15 -08:00
• cbd52c60a8
  
  WIP: next_pc test fails Jacob Lifshay 2025-12-14 01:26:18 -08:00
• c87a1b8e1e
  
  wrote out all of next_pc and tests/next_pc Jacob Lifshay 2025-12-11 00:31:00 -08:00
• cfd04469ce
  
  WIP linking next_pc stages together Jacob Lifshay 2025-12-09 22:36:48 -08:00
• 231f5e72ec
  
  WIP: completed stages of next-pc logic, still need to combine them into a pipeline Jacob Lifshay 2025-12-03 21:27:26 -08:00
• 033d5d4f34
  
  WIP adding next_pc: add call stack Jacob Lifshay 2025-11-28 01:41:18 -08:00
• 7a77c02cda
  
  WIP adding next_pc: added mock_fetch_decode_pipe Jacob Lifshay 2025-10-27 22:41:33 -07:00
• 61d52bd028
  
  add Serialize/Deserialize impls for CpuConfig Jacob Lifshay 2025-10-27 20:25:40 -07:00
• 554238c544
  
  update for new fayalite Jacob Lifshay 2025-11-24 00:57:19 -08:00
• 24d6537ffe
  
  update Fayalite to get new features and bug fixes Jacob Lifshay 2025-10-26 03:43:18 -07:00
• c30bd0737f
  
  add readme Jacob Lifshay 2025-10-24 16:36:31 -07:00
• 291ad59b02
  
  update CI to use new fayalite-deps container Jacob Lifshay 2025-10-23 23:22:37 -07:00
• 5e8bc3e580
  
  upgrade to Fayalite edcc5927a5f9ebca6 Jacob Lifshay 2025-10-23 23:22:27 -07:00
• 0e7a518bd0
  
  switch to use server's new actions org Jacob Lifshay 2025-10-10 00:03:53 -07:00
• 00ddd602c5
  
  format code Jacob Lifshay 2025-08-24 19:08:58 -07:00
• b969249f5f
  
  switch to edition 2024 Jacob Lifshay 2025-08-24 19:07:53 -07:00
• aa50ae543e
  
  upgrade to rust 1.89.0 Jacob Lifshay 2025-08-24 19:06:01 -07:00
• 7de7d5435a
  
  make forgejo actions actually run Jacob Lifshay 2025-08-24 18:50:33 -07:00
• 921cddbe06
  
  disable tests/reg_alloc.rs for now wip-splitting-reg-alloc Jacob Lifshay 2025-03-18 17:26:47 -07:00
• b9d68c0019
  
  WIP: splitting reg_alloc Jacob Lifshay 2025-03-05 23:50:38 -08:00
• 9fa959652e
  
  update fayalite Jacob Lifshay 2025-03-09 22:53:55 -07:00
• 9199fdf35c
  
  add name_mangling_serde crate Jacob Lifshay 2025-03-08 22:34:11 -08:00
• 60341e22af
  
  WIP: add ArrayVec Jacob Lifshay 2025-03-04 00:20:33 -08:00
• 2cfd54ba88
  
  update fayalite to latest git Jacob Lifshay 2025-03-03 22:00:11 -08:00
• ca3bcd7df2
  
  switch CI to use mirrors Jacob Lifshay 2025-03-02 18:04:09 -08:00
• 518284685f
  
  UnitMOp now has L2RegisterFileMOp after renaming and instead has MoveRegMOp before renaming Jacob Lifshay 2025-02-28 17:45:46 -08:00
• 6c91d1b0b0
  
  start adding ROB Jacob Lifshay 2025-02-27 18:22:01 -08:00
• 4ff75313e7
  
  add helper functions for creating instructions Jacob Lifshay 2025-02-23 20:51:44 -08:00
• 5b15f4a6b4
  
  runs instructions that read other instructions' outputs Jacob Lifshay 2025-02-23 19:51:45 -08:00
• 3bd5c77a3f
  
  unit_base is basically finished, implemented AddSub[I], didn't check any tests yet Jacob Lifshay 2025-02-20 20:24:14 -08:00
• 3f6e5cc600
  
  WIP implementing unit_base Jacob Lifshay 2025-02-19 23:54:41 -08:00
• ece788dda3
  
  update fayalite dependency Jacob Lifshay 2025-02-16 20:59:02 -08:00
• 2b7e7e4946
  
  WIP adding unit input/output values and insn tracking Jacob Lifshay 2025-02-13 20:55:43 -08:00
• d7818d889c
  
  update fayalite dependency Jacob Lifshay 2025-02-13 18:52:58 -08:00
• 1084278f34
  
  reg_alloc: add writes to rename table Jacob Lifshay 2025-02-11 19:19:06 -08:00
• 64566f718f
  
  update fayalite to latest git Jacob Lifshay 2025-02-11 16:05:14 -08:00
• 294e979848
  
  tests/reg_alloc: remove simulator debug output Jacob Lifshay 2025-02-06 21:31:05 -08:00
• 7efcd872b5
  
  working on reg_alloc Jacob Lifshay 2025-02-06 21:28:30 -08:00
• 88eff5952b
  
  working on reg_alloc -- wire up free_regs_tracker.alloc_out Jacob Lifshay 2025-01-15 19:47:00 -08:00
• 9781f1f4c5
  
  update to latest fayalite to include bug fix libre-chip/fayalite#16 Jacob Lifshay 2025-01-15 19:14:31 -08:00
• 5f7766777a
  
  working on reg_alloc -- selected_unit_nums should be correct now Jacob Lifshay 2025-01-12 22:11:44 -08:00
• 89717f8916
  
  update to latest version of fayalite Jacob Lifshay 2025-01-09 23:36:23 -08:00
• 24a8b4b71b
  
  update fayalite to latest git Jacob Lifshay 2025-01-09 19:39:25 -08:00
• 12481cfab3
  
  start debugging reg_alloc with simulator Jacob Lifshay 2024-12-20 00:26:16 -08:00
• bf34dee043
  
  update to fayalite commit 9b06019bf54303e51989484a0cfa1641b0e9d543 Jacob Lifshay 2024-12-18 22:36:08 -08:00
• 1761d7094e
  
  update to latest fayalite and match rust version Jacob Lifshay 2024-12-15 20:32:27 -08:00
• b51109f4f6
  
  WIP implementing reg_alloc Jacob Lifshay 2024-11-05 17:34:31 -08:00
• 1a72425156
  
  update fayalite dependency Jacob Lifshay 2024-11-05 17:33:24 -08:00
• 265b5a9cec
  
  add repository to cache key Jacob Lifshay 2024-10-30 20:57:17 -07:00
• 4c94f5d91a
  
  split deps out into separate job with cache and build z3 4.13.3 Jacob Lifshay 2024-10-16 17:03:58 -07:00
• e5f59939cc
  
  remove now-unnecessary memory-based parallelism limiting Jacob Lifshay 2024-10-15 23:51:41 -07:00
• a305ad51b2
  
  reduce formal proof depth to avoid z3 eating all our memory Jacob Lifshay 2024-10-15 23:50:51 -07:00