Actions - libre-chip/cpu - Libre-Chip.org

unit::alu_branch: implement for LogicalFlagsMOp

test.yml #117 -Commit b25448a275 pushed by programmerjake

#14

2026-05-26 06:50:17 +00:00

6m41s

make Unit API work with rename_execute_retire and add a rename_execute_retire test using unit::alu_branch

test.yml #115 -Commit 7151841af5 pushed by programmerjake

master

2026-05-25 05:58:58 +00:00

7m11s

make Unit API work with rename_execute_retire and add a rename_execute_retire test using unit::alu_branch

test.yml #114 -Commit 7151841af5 pushed by programmerjake

#13

2026-05-25 05:36:42 +00:00

6m14s

rename_execute_retire: add reference counting for L1 registers

test.yml #113 -Commit 151683fbda pushed by programmerjake

master

2026-05-22 07:05:35 +00:00

7m20s

rename_execute_retire: add reference counting for L1 registers

test.yml #112 -Commit 151683fbda pushed by programmerjake

#12

2026-05-22 06:48:42 +00:00

6m29s

rename_execute_retire: add reference counting for L2 registers

test.yml #111 -Commit e0dc5d486b pushed by programmerjake

#12

2026-05-22 04:13:14 +00:00

6m3s

implement register fences and use for L2 reg file writes and when running out of L2 reg file output regs

test.yml #109 -Commit bf2cb688c7 pushed by programmerjake

#12

2026-05-22 00:32:46 +00:00

6m25s

rename_execute_retire: generate l2 stores earlier to make more space in units to increase throughput

test.yml #107 -Commit 6026df8d7a pushed by programmerjake

#12

2026-05-21 00:55:07 +00:00

5m45s

tests/rename_execute_retire: add and use mock_combinational_unit

test.yml #106 -Commit 0d69666b00 pushed by programmerjake

#12

2026-05-20 02:40:34 +00:00

6m19s

tests/rename_execute_retire: make loads/stores take more than one cycle to execute

test.yml #105 -Commit 2363e65564 pushed by programmerjake

#12

2026-05-20 01:15:16 +00:00

6m19s

rename_execute_retire: add a `head -n1` test

test.yml #104 -Commit 79ac190093 pushed by programmerjake

#12

2026-05-19 05:32:12 +00:00

9m26s

add TraceAsString around instructions and stuff to make the .vcd files much smaller and easier to read

test.yml #103 -Commit 0d3c41fa14 pushed by programmerjake

#12

2026-05-15 05:45:57 +00:00

5m45s

rename_execute_retire: implement generating L2 reg file writes

test.yml #101 -Commit 3fbdab0862 pushed by programmerjake

#12

2026-05-11 06:52:04 +00:00

12m14s

update decode_one_insn.vcd for modified instruction data structures

test.yml #97 -Commit 409ca7bf97 pushed by programmerjake

#12

2026-05-06 04:57:57 +00:00

5m14s

update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name

test.yml #85 -Commit 6ed04c809e pushed by programmerjake

master

2026-03-27 03:08:42 +00:00

22m6s

update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name

test.yml #84 -Commit 6ed04c809e pushed by programmerjake

#11

2026-03-27 02:46:30 +00:00

21m54s

add sram and main_memory_and_io modules

test.yml #83 -Commit a1147f0f05 pushed by programmerjake

master

2026-03-26 09:50:13 +00:00

23m28s

add sram and main_memory_and_io modules

test.yml #82 -Commit a1147f0f05 pushed by programmerjake

#10

2026-03-26 09:26:26 +00:00

22m26s

add fetch::fetch and fetch::l1_i_cache with some testing

test.yml #80 -Commit e69c92c8da pushed by programmerjake

master

2026-02-22 03:21:03 +00:00

22m40s

add fetch::fetch and fetch::l1_i_cache with some testing

test.yml #79 -Commit e69c92c8da pushed by programmerjake

#9

2026-02-22 02:55:15 +00:00

22m37s

update fayalite to include 1bc835803b for a major speedup of the decoder tests

test.yml #76 -Commit 596440755c pushed by programmerjake

master

2026-02-04 03:27:34 +00:00

24m49s

update fayalite to include 1bc835803b for a major speedup of the decoder tests

test.yml #75 -Commit 596440755c pushed by programmerjake

#8

2026-02-04 03:00:20 +00:00

23m44s

implement decoding mtspr/mfspr/mftb

test.yml #74 -Commit f88346ea37 pushed by programmerjake

master

2026-01-29 02:54:31 +00:00

32m15s

implement decoding mtspr/mfspr/mftb

test.yml #73 -Commit f88346ea37 pushed by programmerjake

#7

2026-01-29 02:07:18 +00:00

31m51s

reduce the number of wires to have one per form/field pair instead of one per insn/field pair

test.yml #71 -Commit faa8dde774 pushed by programmerjake

#7

2026-01-27 00:43:57 +00:00

30m10s

add shift/rotate MOp definition

test.yml #70 -Commit 59874b9b29 pushed by programmerjake

#7

2026-01-26 05:04:43 +00:00

29m25s

implement decoding 8/16/32/64-bit store instructions -- all of Power ISA v3.1c Book I 3.3.3

test.yml #69 -Commit 0824b63d31 pushed by programmerjake

#7

2026-01-25 23:35:07 +00:00

28m0s

implement decoding 8/16/32/64-bit load instructions -- all of Power ISA v3.1C Book I 3.3.2

test.yml #68 -Commit 706d54ae0d pushed by programmerjake

#7

2026-01-24 00:36:14 +00:00

28m7s

make LogicalFlagsMOp also copy the dest PRegValue.flags into PRegValue.int_fp

test.yml #67 -Commit d361a2b578 pushed by programmerjake

#7

2026-01-23 20:40:41 +00:00

27m17s

fix & clean up MOp definitions and ensure_reg_fields_are_in_the_same_place

test.yml #65 -Commit e6f876f9af pushed by programmerjake

#7

2026-01-22 16:57:49 +00:00

28m23s