cesar
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  • Joined on 2024-07-18
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cesar opened issue libre-chip/fayalite#4 2024-11-26 22:44:21 +00:00
Incorrect number of bits for signed range
cesar pushed to formal_test_case at cesar/fayalite 2024-11-20 21:34:53 +00:00
c1f1a8b749 Add test module exercising formal verification.
cesar created pull request libre-chip/fayalite#2 2024-11-20 21:06:31 +00:00
Add test module exercising formal verification.
cesar created branch formal_test_case in cesar/fayalite 2024-11-20 20:47:37 +00:00
cesar pushed to formal_test_case at cesar/fayalite 2024-11-20 20:47:37 +00:00
39d895764a Add test module exercising formal verification.
cesar created repository cesar/fayalite 2024-11-20 20:46:00 +00:00
cesar opened issue libre-chip/fayalite#1 2024-07-22 22:50:27 +00:00
"Register" in Wire Docs