Gather the FIFO debug ports in a bundle

As some proofs involving memories, it is necessary to add more ports to
the queue interface, to sync state. These changes are predicated on the
test environment, so normal use is not affected.

Since some speedup is achieved, use the saved time to test with a deeper
FIFO.

Cargo.lock

@@ -543,9 +543,9 @@ dependencies = [
 
 [[package]]
 name = "proc-macro2"
-version = "1.0.83"
+version = "1.0.92"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0b33eb56c327dec362a9e55b3ad14f9d2f0904fb5a5b03b513ab5465399e9f43"
+checksum = "37d3544b3f2748c54e147655edb5025752e2303145b5aefb3c3ea2c78b973bb0"
 dependencies = [
  "unicode-ident",
 ]
@@ -647,9 +647,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
 [[package]]
 name = "syn"
-version = "2.0.66"
+version = "2.0.93"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cdcff5"
+checksum = "9c786062daee0d6db1132800e623df74274a0a87322d8e183338e01b3d98d058"
 dependencies = [
  "proc-macro2",
  "quote",

Cargo.toml

@@ -37,7 +37,7 @@ quote = "1.0.36"
 serde = { version = "1.0.202", features = ["derive"] }
 serde_json = { version = "1.0.117", features = ["preserve_order"] }
 sha2 = "0.10.8"
-syn = { version = "2.0.66", features = ["full", "fold", "visit", "extra-traits"] }
+syn = { version = "2.0.93", features = ["full", "fold", "visit", "extra-traits"] }
 tempfile = "3.10.1"
 thiserror = "1.0.61"
 trybuild = "1.0"

crates/fayalite-proc-macros-impl/src/lib.rs

@@ -3,14 +3,20 @@
 #![cfg_attr(test, recursion_limit = "512")]
 use proc_macro2::{Span, TokenStream};
 use quote::{quote, ToTokens};
-use std::io::{ErrorKind, Write};
+use std::{
+    collections::{hash_map::Entry, HashMap},
+    io::{ErrorKind, Write},
+};
 use syn::{
-    bracketed, parenthesized,
+    bracketed,
+    ext::IdentExt,
+    parenthesized,
     parse::{Parse, ParseStream, Parser},
     parse_quote,
-    punctuated::Pair,
+    punctuated::{Pair, Punctuated},
     spanned::Spanned,
-    AttrStyle, Attribute, Error, Item, ItemFn, Token,
+    token::{Bracket, Paren},
+    AttrStyle, Attribute, Error, Ident, Item, ItemFn, LitBool, LitStr, Meta, Token,
 };
 
 mod fold;
@@ -19,6 +25,7 @@ mod hdl_enum;
 mod hdl_type_alias;
 mod hdl_type_common;
 mod module;
+mod process_cfg;
 
 pub(crate) trait CustomToken:
     Copy
@@ -59,6 +66,11 @@ mod kw {
         };
     }
 
+    custom_keyword!(__evaluated_cfgs);
+    custom_keyword!(all);
+    custom_keyword!(any);
+    custom_keyword!(cfg);
+    custom_keyword!(cfg_attr);
     custom_keyword!(clock_domain);
     custom_keyword!(connect_inexact);
     custom_keyword!(custom_bounds);
@@ -75,6 +87,7 @@ mod kw {
     custom_keyword!(no_reset);
     custom_keyword!(no_runtime_generics);
     custom_keyword!(no_static);
+    custom_keyword!(not);
     custom_keyword!(outline_generated);
     custom_keyword!(output);
     custom_keyword!(reg_builder);
@@ -901,15 +914,346 @@ fn hdl_module_impl(item: ItemFn) -> syn::Result<TokenStream> {
     Ok(contents)
 }
 
-pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let kw = kw::hdl_module::default();
-    hdl_module_impl(syn::parse2(quote! { #[#kw(#attr)] #item })?)
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) enum CfgExpr {
+    Option {
+        ident: Ident,
+        value: Option<(Token![=], LitStr)>,
+    },
+    All {
+        all: kw::all,
+        paren: Paren,
+        exprs: Punctuated<CfgExpr, Token![,]>,
+    },
+    Any {
+        any: kw::any,
+        paren: Paren,
+        exprs: Punctuated<CfgExpr, Token![,]>,
+    },
+    Not {
+        not: kw::not,
+        paren: Paren,
+        expr: Box<CfgExpr>,
+        trailing_comma: Option<Token![,]>,
+    },
 }
 
-pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let kw = kw::hdl::default();
-    let item = quote! { #[#kw(#attr)] #item };
-    let item = syn::parse2::<Item>(item)?;
+impl Parse for CfgExpr {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        match input.cursor().ident() {
+            Some((_, cursor)) if cursor.eof() => {
+                return Ok(CfgExpr::Option {
+                    ident: input.call(Ident::parse_any)?,
+                    value: None,
+                });
+            }
+            _ => {}
+        }
+        if input.peek(Ident::peek_any) && input.peek2(Token![=]) {
+            return Ok(CfgExpr::Option {
+                ident: input.call(Ident::parse_any)?,
+                value: Some((input.parse()?, input.parse()?)),
+            });
+        }
+        let contents;
+        if input.peek(kw::all) {
+            Ok(CfgExpr::All {
+                all: input.parse()?,
+                paren: parenthesized!(contents in input),
+                exprs: contents.call(Punctuated::parse_terminated)?,
+            })
+        } else if input.peek(kw::any) {
+            Ok(CfgExpr::Any {
+                any: input.parse()?,
+                paren: parenthesized!(contents in input),
+                exprs: contents.call(Punctuated::parse_terminated)?,
+            })
+        } else if input.peek(kw::not) {
+            Ok(CfgExpr::Not {
+                not: input.parse()?,
+                paren: parenthesized!(contents in input),
+                expr: contents.parse()?,
+                trailing_comma: contents.parse()?,
+            })
+        } else {
+            Err(input.error("expected cfg-pattern"))
+        }
+    }
+}
+
+impl ToTokens for CfgExpr {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        match self {
+            CfgExpr::Option { ident, value } => {
+                ident.to_tokens(tokens);
+                if let Some((eq, value)) = value {
+                    eq.to_tokens(tokens);
+                    value.to_tokens(tokens);
+                }
+            }
+            CfgExpr::All { all, paren, exprs } => {
+                all.to_tokens(tokens);
+                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
+            }
+            CfgExpr::Any { any, paren, exprs } => {
+                any.to_tokens(tokens);
+                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
+            }
+            CfgExpr::Not {
+                not,
+                paren,
+                expr,
+                trailing_comma,
+            } => {
+                not.to_tokens(tokens);
+                paren.surround(tokens, |tokens| {
+                    expr.to_tokens(tokens);
+                    trailing_comma.to_tokens(tokens);
+                });
+            }
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct Cfg {
+    cfg: kw::cfg,
+    paren: Paren,
+    expr: CfgExpr,
+    trailing_comma: Option<Token![,]>,
+}
+
+impl Cfg {
+    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
+        syn::parse2(meta.to_token_stream())
+    }
+}
+
+impl ToTokens for Cfg {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            cfg,
+            paren,
+            expr,
+            trailing_comma,
+        } = self;
+        cfg.to_tokens(tokens);
+        paren.surround(tokens, |tokens| {
+            expr.to_tokens(tokens);
+            trailing_comma.to_tokens(tokens);
+        });
+    }
+}
+
+impl Parse for Cfg {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        Ok(Self {
+            cfg: input.parse()?,
+            paren: parenthesized!(contents in input),
+            expr: contents.parse()?,
+            trailing_comma: contents.parse()?,
+        })
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct CfgAttr {
+    cfg_attr: kw::cfg_attr,
+    paren: Paren,
+    expr: CfgExpr,
+    comma: Token![,],
+    attrs: Punctuated<Meta, Token![,]>,
+}
+
+impl CfgAttr {
+    pub(crate) fn to_cfg(&self) -> Cfg {
+        Cfg {
+            cfg: kw::cfg(self.cfg_attr.span),
+            paren: self.paren,
+            expr: self.expr.clone(),
+            trailing_comma: None,
+        }
+    }
+    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
+        syn::parse2(meta.to_token_stream())
+    }
+}
+
+impl Parse for CfgAttr {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        Ok(Self {
+            cfg_attr: input.parse()?,
+            paren: parenthesized!(contents in input),
+            expr: contents.parse()?,
+            comma: contents.parse()?,
+            attrs: contents.call(Punctuated::parse_terminated)?,
+        })
+    }
+}
+
+pub(crate) struct CfgAndValue {
+    cfg: Cfg,
+    eq_token: Token![=],
+    value: LitBool,
+}
+
+impl Parse for CfgAndValue {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        Ok(Self {
+            cfg: input.parse()?,
+            eq_token: input.parse()?,
+            value: input.parse()?,
+        })
+    }
+}
+
+pub(crate) struct Cfgs<T> {
+    pub(crate) bracket: Bracket,
+    pub(crate) cfgs_map: HashMap<Cfg, T>,
+    pub(crate) cfgs_list: Vec<Cfg>,
+}
+
+impl<T> Default for Cfgs<T> {
+    fn default() -> Self {
+        Self {
+            bracket: Default::default(),
+            cfgs_map: Default::default(),
+            cfgs_list: Default::default(),
+        }
+    }
+}
+
+impl<T> Cfgs<T> {
+    fn insert_cfg(&mut self, cfg: Cfg, value: T) {
+        match self.cfgs_map.entry(cfg) {
+            Entry::Occupied(_) => {}
+            Entry::Vacant(entry) => {
+                self.cfgs_list.push(entry.key().clone());
+                entry.insert(value);
+            }
+        }
+    }
+}
+
+impl Parse for Cfgs<bool> {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        let bracket = bracketed!(contents in input);
+        let mut cfgs_map = HashMap::new();
+        let mut cfgs_list = Vec::new();
+        for CfgAndValue {
+            cfg,
+            eq_token,
+            value,
+        } in contents.call(Punctuated::<CfgAndValue, Token![,]>::parse_terminated)?
+        {
+            let _ = eq_token;
+            match cfgs_map.entry(cfg) {
+                Entry::Occupied(_) => {}
+                Entry::Vacant(entry) => {
+                    cfgs_list.push(entry.key().clone());
+                    entry.insert(value.value);
+                }
+            }
+        }
+        Ok(Self {
+            bracket,
+            cfgs_map,
+            cfgs_list,
+        })
+    }
+}
+
+impl Parse for Cfgs<()> {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        let bracket = bracketed!(contents in input);
+        let mut cfgs_map = HashMap::new();
+        let mut cfgs_list = Vec::new();
+        for cfg in contents.call(Punctuated::<Cfg, Token![,]>::parse_terminated)? {
+            match cfgs_map.entry(cfg) {
+                Entry::Occupied(_) => {}
+                Entry::Vacant(entry) => {
+                    cfgs_list.push(entry.key().clone());
+                    entry.insert(());
+                }
+            }
+        }
+        Ok(Self {
+            bracket,
+            cfgs_map,
+            cfgs_list,
+        })
+    }
+}
+
+impl ToTokens for Cfgs<()> {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            bracket,
+            cfgs_map: _,
+            cfgs_list,
+        } = self;
+        bracket.surround(tokens, |tokens| {
+            for cfg in cfgs_list {
+                cfg.to_tokens(tokens);
+                <Token![,]>::default().to_tokens(tokens);
+            }
+        });
+    }
+}
+
+fn hdl_main(
+    kw: impl CustomToken,
+    attr: TokenStream,
+    item: TokenStream,
+) -> syn::Result<TokenStream> {
+    fn parse_evaluated_cfgs_attr<R>(
+        input: ParseStream,
+        parse_inner: impl FnOnce(ParseStream) -> syn::Result<R>,
+    ) -> syn::Result<R> {
+        let _: Token![#] = input.parse()?;
+        let bracket_content;
+        bracketed!(bracket_content in input);
+        let _: kw::__evaluated_cfgs = bracket_content.parse()?;
+        let paren_content;
+        parenthesized!(paren_content in bracket_content);
+        parse_inner(&paren_content)
+    }
+    let (evaluated_cfgs, item): (_, TokenStream) = Parser::parse2(
+        |input: ParseStream| {
+            let peek = input.fork();
+            if parse_evaluated_cfgs_attr(&peek, |_| Ok(())).is_ok() {
+                let evaluated_cfgs = parse_evaluated_cfgs_attr(input, Cfgs::<bool>::parse)?;
+                Ok((Some(evaluated_cfgs), input.parse()?))
+            } else {
+                Ok((None, input.parse()?))
+            }
+        },
+        item,
+    )?;
+    let cfgs = if let Some(cfgs) = evaluated_cfgs {
+        cfgs
+    } else {
+        let cfgs = process_cfg::collect_cfgs(syn::parse2(item.clone())?)?;
+        if cfgs.cfgs_list.is_empty() {
+            Cfgs::default()
+        } else {
+            return Ok(quote! {
+                ::fayalite::__cfg_expansion_helper! {
+                    []
+                    #cfgs
+                    {#[::fayalite::#kw(#attr)]} { #item }
+                }
+            });
+        }
+    };
+    let item = syn::parse2(quote! { #[#kw(#attr)] #item })?;
+    let Some(item) = process_cfg::process_cfgs(item, cfgs)? else {
+        return Ok(TokenStream::new());
+    };
     match item {
         Item::Enum(item) => hdl_enum::hdl_enum(item),
         Item::Struct(item) => hdl_bundle::hdl_bundle(item),
@@ -921,3 +1265,11 @@ pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream
         )),
     }
 }
+
+pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
+    hdl_main(kw::hdl_module::default(), attr, item)
+}
+
+pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
+    hdl_main(kw::hdl::default(), attr, item)
+}

crates/fayalite/build.rs

@@ -5,6 +5,9 @@ use std::{env, fs, path::Path};
 
 fn main() {
     println!("cargo::rustc-check-cfg=cfg(todo)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_false_for_tests)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_true_for_tests)");
+    println!("cargo::rustc-cfg=cfg_true_for_tests");
     let path = "visit_types.json";
     println!("cargo::rerun-if-changed={path}");
     println!("cargo::rerun-if-changed=build.rs");

crates/fayalite/src/lib.rs

@@ -11,6 +11,59 @@ extern crate self as fayalite;
 #[doc(hidden)]
 pub use std as __std;
 
+#[doc(hidden)]
+#[macro_export]
+macro_rules! __cfg_expansion_helper {
+    (
+        [
+            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
+        ]
+        [
+            $cfg:ident($($expr:tt)*),
+            $($unevaluated_cfgs:ident($($unevaluated_exprs:tt)*),)*
+        ]
+        // pass as tt so we get right span for attribute
+        $after_evaluation_attr:tt $after_evaluation_body:tt
+    ) => {
+        #[$cfg($($expr)*)]
+        $crate::__cfg_expansion_helper! {
+            [
+                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+                $cfg($($expr)*) = true,
+            ]
+            [
+                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
+            ]
+            $after_evaluation_attr $after_evaluation_body
+        }
+        #[$cfg(not($($expr)*))]
+        $crate::__cfg_expansion_helper! {
+            [
+                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+                $cfg($($expr)*) = false,
+            ]
+            [
+                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
+            ]
+            $after_evaluation_attr $after_evaluation_body
+        }
+    };
+    (
+        [
+            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
+        ]
+        []
+        // don't use #[...] so we get right span for `#` and `[]` of attribute
+        {$($after_evaluation_attr:tt)*} {$($after_evaluation_body:tt)*}
+    ) => {
+        $($after_evaluation_attr)*
+        #[__evaluated_cfgs([
+            $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+        ])]
+        $($after_evaluation_body)*
+    };
+}
+
 #[doc(inline)]
 /// The `#[hdl_module]` attribute is applied to a Rust function so that that function creates
 /// a [`Module`][`::fayalite::module::Module`] when called.

crates/fayalite/src/util/ready_valid.rs

@@ -49,6 +49,18 @@ impl<T: Type> ReadyValid<T> {
     }
 }
 
+/// This debug port is only meant to assist the formal proof of the queue.
+#[cfg(test)]
+#[doc(hidden)]
+#[hdl]
+pub struct QueueDebugPort<Element, Index> {
+    #[hdl(flip)]
+    index_to_check: Index,
+    stored: Element,
+    inp_index: Index,
+    out_index: Index,
+}
+
 #[hdl_module]
 pub fn queue<T: Type>(
     ty: T,
@@ -178,6 +190,22 @@ pub fn queue<T: Type>(
             }
         }
     }
+    // These debug ports expose some internal state during the Induction phase
+    // of Formal Verification. They are not present in normal use.
+    #[cfg(test)]
+    {
+        #[hdl]
+        let dbg: QueueDebugPort<T, UInt> = m.output(QueueDebugPort[ty][index_ty]);
+        // read the memory word currently stored at some fixed index
+        let debug_port = mem.new_read_port();
+        connect(debug_port.addr, dbg.index_to_check);
+        connect(debug_port.en, true);
+        connect(debug_port.clk, cd.clk);
+        connect(dbg.stored, debug_port.data);
+        // also expose the current read and write indices
+        connect(dbg.inp_index, inp_index_reg);
+        connect(dbg.out_index, out_index_reg);
+    }
 }
 
 #[cfg(test)]
@@ -196,13 +224,23 @@ mod tests {
             format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
             queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
             FormalMode::Prove,
-            14,
+            2,
             None,
             ExportOptions {
                 simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
                 ..ExportOptions::default()
             },
         );
+        /// Formal verification of the FIFO queue
+        ///
+        /// The strategy derives from the observation that, if we filter its
+        /// input and output streams to consider just one in every N reads and
+        /// writes (where N is the FIFO capacity), then the FIFO effectively
+        /// behaves as a one-entry FIFO.
+        ///
+        /// In particular, any counterexample of the full FIFO behaving badly
+        /// will also be caught by one of the filtered versions (one which
+        /// happens to be in phase with the offending input or output).
         #[hdl_module]
         fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
             #[hdl]
@@ -217,6 +255,8 @@ mod tests {
                     rst: formal_reset().to_reset(),
                 },
             );
+
+            // random input data
             #[hdl]
             let inp_data: HdlOption<UInt<8>> = wire();
             #[hdl]
@@ -225,16 +265,26 @@ mod tests {
             } else {
                 connect(inp_data, HdlNone());
             }
+
+            // assert output ready at random
             #[hdl]
             let out_ready: Bool = wire();
             connect(out_ready, any_seq(Bool));
-            let index_ty: UInt<32> = UInt::TYPE;
+
+            // The current number of elements in the FIFO ranges from zero to
+            // maximum capacity, inclusive.
+            let count_ty = UInt::range_inclusive(0..=capacity.get());
+            // type for counters that wrap around at the FIFO capacity
+            let index_ty = UInt::range(0..capacity.get());
+
+            // among all entries of the FIFO internal circular memory, choose
+            // one at random to check
             #[hdl]
-            let index_to_check = wire();
+            let index_to_check = wire(index_ty);
             connect(index_to_check, any_const(index_ty));
-            let index_max = !index_ty.zero();
-            // we saturate at index_max, so only check indexes where we properly maintain position
-            hdl_assume(clk, index_to_check.cmp_ne(index_max), "");
+            hdl_assume(clk, index_to_check.cmp_lt(capacity.get()), "");
+
+            // instantiate and connect the queue
             #[hdl]
             let dut = instance(queue(
                 UInt[ConstUsize::<8>],
@@ -245,109 +295,172 @@ mod tests {
             connect(dut.cd, cd);
             connect(dut.inp.data, inp_data);
             connect(dut.out.ready, out_ready);
-            hdl_assume(
-                clk,
-                index_to_check.cmp_ne(!Expr::ty(index_to_check).zero()),
-                "",
-            );
 
+            // Keep an independent count of words in the FIFO. Ensure that
+            // it's always correct, and never overflows.
             #[hdl]
-            let expected_count_reg = reg_builder().clock_domain(cd).reset(0u32);
-            #[hdl]
-            let next_expected_count = wire();
-            connect(next_expected_count, expected_count_reg);
-            connect(expected_count_reg, next_expected_count);
+            let expected_count_reg = reg_builder().clock_domain(cd).reset(count_ty.zero());
             #[hdl]
             if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) {
-                connect_any(next_expected_count, expected_count_reg + 1u8);
+                hdl_assert(clk, expected_count_reg.cmp_ne(capacity.get()), "");
+                connect_any(expected_count_reg, expected_count_reg + 1u8);
             } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) {
-                connect_any(next_expected_count, expected_count_reg - 1u8);
+                hdl_assert(clk, expected_count_reg.cmp_ne(count_ty.zero()), "");
+                connect_any(expected_count_reg, expected_count_reg - 1u8);
             }
-            hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
-
-            #[hdl]
-            let prev_out_ready_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
-            connect_any(
-                prev_out_ready_reg,
-                (prev_out_ready_reg << 1) | out_ready.cast_to(UInt[1]),
-            );
-            #[hdl]
-            let prev_inp_valid_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
-            connect_any(
-                prev_inp_valid_reg,
-                (prev_inp_valid_reg << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
-            );
-            hdl_assume(
-                clk,
-                (prev_out_ready_reg & prev_inp_valid_reg).cmp_ne(0u8),
-                "",
-            );
+            hdl_assert(clk, expected_count_reg.cmp_eq(dut.count), "");
 
+            // keep an independent write index into the FIFO's circular buffer
             #[hdl]
             let inp_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
-
-            #[hdl]
-            if let HdlSome(data) = ReadyValid::firing_data(dut.inp) {
+            if ReadyValid::firing(dut.inp) {
                 #[hdl]
-                if inp_index_reg.cmp_lt(index_max) {
+                if inp_index_reg.cmp_ne(capacity.get() - 1) {
                     connect_any(inp_index_reg, inp_index_reg + 1u8);
-                    #[hdl]
-                    if inp_index_reg.cmp_eq(index_to_check) {
-                        connect(stored_inp_data_reg, data);
-                    }
+                } else {
+                    connect_any(inp_index_reg, 0_hdl_u0);
                 }
             }
 
-            #[hdl]
-            if inp_index_reg.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_inp_data_reg.cmp_eq(0u8), "");
-            }
-
+            // keep an independent read index into the FIFO's circular buffer
             #[hdl]
             let out_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
-
-            #[hdl]
-            if let HdlSome(data) = ReadyValid::firing_data(dut.out) {
+            if ReadyValid::firing(dut.out) {
                 #[hdl]
-                if out_index_reg.cmp_lt(index_max) {
+                if out_index_reg.cmp_ne(capacity.get() - 1) {
                     connect_any(out_index_reg, out_index_reg + 1u8);
+                } else {
+                    connect_any(out_index_reg, 0_hdl_u0);
+                }
+            }
+
+            // filter the input data stream, predicated by the read index
+            // matching the chosen position in the FIFO's circular buffer
+            #[hdl]
+            let inp_index_matches = wire();
+            connect(inp_index_matches, inp_index_reg.cmp_eq(index_to_check));
+            #[hdl]
+            let inp_firing_data = wire();
+            connect(inp_firing_data, HdlNone());
+            #[hdl]
+            if inp_index_matches {
+                connect(inp_firing_data, ReadyValid::firing_data(dut.inp));
+            }
+
+            // filter the output data stream, predicated by the write index
+            // matching the chosen position in the FIFO's circular buffer
+            #[hdl]
+            let out_index_matches = wire();
+            connect(out_index_matches, out_index_reg.cmp_eq(index_to_check));
+            #[hdl]
+            let out_firing_data = wire();
+            connect(out_firing_data, HdlNone());
+            #[hdl]
+            if out_index_matches {
+                connect(out_firing_data, ReadyValid::firing_data(dut.out));
+            }
+
+            // Implement a one-entry FIFO and ensure its equivalence to the
+            // filtered FIFO.
+            //
+            // the holding register for our one-entry FIFO
+            #[hdl]
+            let stored_reg = reg_builder().clock_domain(cd).reset(HdlNone());
+            #[hdl]
+            match stored_reg {
+                // If the holding register is empty...
+                HdlNone => {
                     #[hdl]
-                    if out_index_reg.cmp_eq(index_to_check) {
-                        connect(stored_out_data_reg, data);
+                    match inp_firing_data {
+                        // ... and we are not receiving data, then we must not
+                        // transmit any data.
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(out_firing_data), ""),
+                        // If we are indeed receiving some data...
+                        HdlSome(data_in) => {
+                            #[hdl]
+                            match out_firing_data {
+                                // ... and transmitting at the same time, we
+                                // must be transmitting the input data itself,
+                                // since the holding register is empty.
+                                HdlSome(data_out) => hdl_assert(clk, data_out.cmp_eq(data_in), ""),
+                                // If we are receiving, but not transmitting,
+                                // store the received data in the holding
+                                // register.
+                                HdlNone => connect(stored_reg, HdlSome(data_in)),
+                            }
+                        }
+                    }
+                }
+                // If there is some value stored in the holding register...
+                HdlSome(stored) => {
+                    #[hdl]
+                    match out_firing_data {
+                        // ... and we are not transmitting it, we cannot
+                        // receive any more data.
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(inp_firing_data), ""),
+                        // If we are transmitting a previously stored value...
+                        HdlSome(data_out) => {
+                            // ... it must be the same data we stored earlier.
+                            hdl_assert(clk, data_out.cmp_eq(stored), "");
+                            // Also, accept new data, if any. Otherwise,
+                            // let the holding register become empty.
+                            connect(stored_reg, inp_firing_data);
+                        }
                     }
                 }
             }
 
+            // from now on, some extra assertions in order to pass induction
+
+            // sync the holding register, when it's occupied, to the
+            // corresponding entry in the FIFO's circular buffer
+            connect(dut.dbg.index_to_check, index_to_check);
             #[hdl]
-            if out_index_reg.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_out_data_reg.cmp_eq(0u8), "");
+            if let HdlSome(stored) = stored_reg {
+                hdl_assert(clk, stored.cmp_eq(dut.dbg.stored), "");
             }
 
-            hdl_assert(clk, inp_index_reg.cmp_ge(out_index_reg), "");
+            // sync the read and write indices
+            hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), "");
+            hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg.out_index), "");
 
+            // the indices should never go past the capacity, but induction
+            // doesn't know that...
+            hdl_assert(clk, inp_index_reg.cmp_lt(capacity.get()), "");
+            hdl_assert(clk, out_index_reg.cmp_lt(capacity.get()), "");
+
+            // strongly constrain the state of the holding register
+            //
+            // The holding register is full if and only if the corresponding
+            // FIFO entry was written to and not yet read. In other words, if
+            // the number of pending reads until the chosen entry is read out
+            // is greater than the current FIFO count, then the entry couldn't
+            // be in the FIFO in the first place.
             #[hdl]
-            if inp_index_reg.cmp_lt(index_max) & out_index_reg.cmp_lt(index_max) {
-                hdl_assert(
-                    clk,
-                    expected_count_reg.cmp_eq(inp_index_reg - out_index_reg),
-                    "",
-                );
+            let pending_reads: UInt = wire(index_ty);
+            // take care of wrap-around when subtracting indices, add the
+            // capacity amount to keep the result positive if necessary
+            #[hdl]
+            if index_to_check.cmp_ge(out_index_reg) {
+                connect(pending_reads, index_to_check - out_index_reg);
             } else {
-                hdl_assert(
-                    clk,
-                    expected_count_reg.cmp_ge(inp_index_reg - out_index_reg),
-                    "",
+                connect(
+                    pending_reads,
+                    index_to_check + capacity.get() - out_index_reg,
                 );
             }
-
+            // check whether the chosen entry is in the FIFO
             #[hdl]
-            if inp_index_reg.cmp_gt(index_to_check) & out_index_reg.cmp_gt(index_to_check) {
-                hdl_assert(clk, stored_inp_data_reg.cmp_eq(stored_out_data_reg), "");
-            }
+            let expected_stored: Bool = wire();
+            connect(expected_stored, pending_reads.cmp_lt(dut.count));
+            // sync with the state of the holding register
+            hdl_assert(
+                clk,
+                expected_stored.cmp_eq(HdlOption::is_some(stored_reg)),
+                "",
+            );
         }
     }
 
@@ -430,4 +543,24 @@ mod tests {
     fn test_4_true_true() {
         test_queue(NonZero::new(4).unwrap(), true, true);
     }
+
+    #[test]
+    fn test_many_false_false() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, false);
+    }
+
+    #[test]
+    fn test_many_false_true() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, true);
+    }
+
+    #[test]
+    fn test_many_true_false() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, false);
+    }
+
+    #[test]
+    fn test_many_true_true() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, true);
+    }
 }

crates/fayalite/tests/module.rs

@@ -4287,3 +4287,61 @@ circuit check_deduce_resets:
 ",
     };
 }
+
+// intentionally not outline_generated to ensure we get correct macro hygiene
+#[hdl_module]
+pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
+    #[cfg(cfg_false_for_tests)] a: A,
+    #[cfg(cfg_true_for_tests)] b: B,
+) {
+    #[hdl]
+    struct S<#[cfg(cfg_false_for_tests)] A, #[cfg(cfg_true_for_tests)] B> {
+        #[cfg(cfg_false_for_tests)]
+        a: A,
+        #[cfg(cfg_true_for_tests)]
+        b: B,
+    }
+    #[hdl]
+    #[cfg(cfg_false_for_tests)]
+    let i_a: A = m.input(a);
+    #[hdl]
+    #[cfg(cfg_true_for_tests)]
+    let i_b: B = m.input(b);
+    #[hdl]
+    let w: S<UInt<8>> = wire();
+    #[cfg(cfg_false_for_tests)]
+    {
+        #[hdl]
+        let o_a: A = m.output(a);
+        connect(o_a, w.a.cast_bits_to(a));
+        connect_any(w.a, i_a.cast_to_bits());
+    }
+    #[cfg(cfg_true_for_tests)]
+    {
+        #[hdl]
+        let o_b: B = m.output(b);
+        connect(o_b, w.b.cast_bits_to(b));
+        connect_any(w.b, i_b.cast_to_bits());
+    }
+}
+
+#[test]
+fn test_cfgs() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_cfgs(UInt[8]);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_cfgs.fir": r"FIRRTL version 3.2.0
+circuit check_cfgs:
+    type Ty0 = {b: UInt<8>}
+    module check_cfgs: @[the_test_file.rs 9962:1]
+        input i_b: UInt<8> @[the_test_file.rs 9979:20]
+        output o_b: UInt<8> @[the_test_file.rs 9992:24]
+        wire w: Ty0 @[the_test_file.rs 9981:25]
+        connect o_b, w.b @[the_test_file.rs 9993:9]
+        connect w.b, i_b @[the_test_file.rs 9994:9]
+",
+    };
+}