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Author	SHA1	Message	Date
Jacob Lifshay	b25448a275	unit::alu_branch: implement for LogicalFlagsMOp	2026-05-25 23:42:57 -07:00
Jacob Lifshay	99c019431b	unit::alu_branch: implement for ShiftRotateMOp; TODO: flags and shift amount overflow	2026-05-25 23:15:43 -07:00
Jacob Lifshay	dd2fe36869	rename_execute_retire: add more tests using unit::alu_branch	2026-05-25 21:31:43 -07:00
Jacob Lifshay	225ceb0dfa	unit::alu_branch: implement for CompareMOp	2026-05-25 18:49:04 -07:00
Jacob Lifshay	67abfa2f5d	unit::alu_branch::add_sub: x86 CF and AF are used as borrow flags for subtraction	2026-05-25 18:48:59 -07:00
Jacob Lifshay	5558763718	rename test_rename_execute_retire_real_alu_branch -> test_rename_execute_retire_save_restore_gprs_real	2026-05-25 18:35:59 -07:00
Jacob Lifshay	7151841af5	make Unit API work with rename_execute_retire and add a rename_execute_retire test using unit::alu_branch	2026-05-24 22:23:23 -07:00
Jacob Lifshay	a88009a303	add GlobalState to ExecuteToUnitInterface	2026-05-24 19:56:14 -07:00
Jacob Lifshay	ce8519b2db	util: add and use checked_vcd_output	2026-05-24 19:49:10 -07:00
Jacob Lifshay	151683fbda	rename_execute_retire: add reference counting for L1 registers	2026-05-21 23:41:11 -07:00
Jacob Lifshay	e0dc5d486b	rename_execute_retire: add reference counting for L2 registers	2026-05-21 21:06:40 -07:00
Jacob Lifshay	fdf1e97e10	move RenameTable and ReorderBuffer into their own mods	2026-05-21 20:46:19 -07:00
Jacob Lifshay	bf2cb688c7	implement register fences and use for L2 reg file writes and when running out of L2 reg file output regs ... fixes deadlock when running rename_execute_retire_save_restore_gprs	2026-05-21 17:23:57 -07:00
Jacob Lifshay	3e08a282ec	add test_rename_execute_retire_save_restore_gprs ... currently it fails due to the L2 reg file running out of output registers	2026-05-20 19:44:20 -07:00
Jacob Lifshay	6026df8d7a	rename_execute_retire: generate l2 stores earlier to make more space in units to increase throughput	2026-05-20 17:02:34 -07:00
Jacob Lifshay	e502dfe574	rename_execute_retire: don't include completed instructions in space used by a unit	2026-05-20 16:56:58 -07:00
Jacob Lifshay	0d69666b00	tests/rename_execute_retire: add and use mock_combinational_unit	2026-05-19 19:33:09 -07:00
Jacob Lifshay	2363e65564	tests/rename_execute_retire: make loads/stores take more than one cycle to execute	2026-05-19 18:08:07 -07:00
Jacob Lifshay	79ac190093	rename_execute_retire: add a head -n1 test	2026-05-18 22:22:31 -07:00
Jacob Lifshay	0d3c41fa14	add TraceAsString around instructions and stuff to make the .vcd files much smaller and easier to read	2026-05-14 22:38:50 -07:00
Jacob Lifshay	8bee576a2a	update fayalite to get TraceAsString	2026-05-14 22:28:25 -07:00
Jacob Lifshay	3fbdab0862	rename_execute_retire: implement generating L2 reg file writes	2026-05-10 23:39:02 -07:00
Jacob Lifshay	33b5d59507	improve debug formatting of PRegValue and PRegFlags	2026-05-07 21:40:23 -07:00
Jacob Lifshay	559e2967a2	improve debug formatting of MOpRegNum/MOpDestReg	2026-05-07 21:25:27 -07:00
Jacob Lifshay	5e6041a97c	change MOp to use SrcReg: Type instead of UIntType<SrcRegWidth>	2026-05-07 19:56:56 -07:00
Jacob Lifshay	409ca7bf97	update decode_one_insn.vcd for modified instruction data structures	2026-05-05 21:52:02 -07:00
Jacob Lifshay	9308e5d195	update fayalite to fix bug in VCD generation	2026-05-05 21:28:46 -07:00
Jacob Lifshay	09c8c194e0	group micro ops by the instruction they come from when retiring	2026-05-05 19:33:25 -07:00
Jacob Lifshay	83b3f7bac9	use custom debug	2026-05-03 23:35:19 -07:00
Jacob Lifshay	ba9ec3bd29	adapt code for new fayalite features	2026-05-03 23:35:19 -07:00
Jacob Lifshay	1229d9c758	update fayalite for optimizations and new features	2026-05-03 23:35:19 -07:00
Jacob Lifshay	283117d8df	add support for speculative loads	2026-04-30 17:51:33 -07:00
Jacob Lifshay	4d21ca622b	add initial impl of rename_execute_retire; running a recursive fibonacci gives the correct output	2026-04-24 18:13:27 -07:00
Jacob Lifshay	6ed04c809e	update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name	2026-03-26 19:21:52 -07:00
Jacob Lifshay	a1147f0f05	add sram and main_memory_and_io modules	2026-03-26 02:03:06 -07:00
Jacob Lifshay	5bdc71acc3	add memory_interface_adapter_no_split	2026-03-26 02:03:06 -07:00
Jacob Lifshay	a15367c37e	add address_range to MemoryInterfaceConfig and add support to simple_uart	2026-03-24 23:46:46 -07:00
Jacob Lifshay	0d451e4e95	change MemoryInterface types to have their own config	2026-03-24 23:46:46 -07:00
Jacob Lifshay	689b4ef65a	implement simple_uart::simple_uart	2026-03-24 23:46:46 -07:00
Jacob Lifshay	79eac8929a	add test for simple_uart::receiver	2026-03-24 23:46:46 -07:00
Jacob Lifshay	f372190b68	add main_memory_and_io::simple_uart::receiver* and test for receiver_no_queue	2026-03-24 23:46:46 -07:00
Jacob Lifshay	e31375b9ce	add main_memory_and_io::simple_uart::{transmitter, uart_clock_gen} and tests	2026-03-24 23:46:46 -07:00
Jacob Lifshay	4ffaba8840	add MemoryOperationStart.rw_mask	2026-03-24 23:46:46 -07:00
Jacob Lifshay	4de29dd16e	move MemoryInterface and related types to crate::main_memory_and_io	2026-03-24 23:46:46 -07:00
Jacob Lifshay	245b872cf7	update to latest fayalite	2026-03-24 23:46:46 -07:00
Jacob Lifshay	e69c92c8da	add fetch::fetch and fetch::l1_i_cache with some testing	2026-02-21 18:32:01 -08:00
Jacob Lifshay	c62d33048c	update fayalite to c632e5d570 to speed up simulation	2026-02-04 16:33:46 -08:00
Jacob Lifshay	596440755c	update fayalite to include 1bc835803b for a major speedup of the decoder tests	2026-02-03 18:17:31 -08:00
Jacob Lifshay	68a4373bbd	update rust version to 1.93.0	2026-02-03 18:17:18 -08:00
Jacob Lifshay	f88346ea37	implement decoding mtspr/mfspr/mftb	2026-01-28 17:35:09 -08:00